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A 32-bit Pipelined Carry-select Adder Using the Complementary Scheme  

Kim, Young-Joon (Division of Electrical Engineering, Dept. of Electrical Engineering & Computer Science, KAIST)
Kim, Lee-Sup (Division of Electrical Engineering, Dept. of Electrical Engineering & Computer Science, KAIST)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.9, 2002 , pp. 55-61 More about this Journal
Abstract
Using the carry-select adder scheme, an adder with small number of stages can be operated as fast as an adder with large number of stages. In this paper, a 4-block 5-stage 32-bit pipelined carry-select adder is designed and implemented. The proposed adder operates as fast as a conventional 16-stage 32-bit pipelined adder while the number of registers required is nearly same as a conventional 4-stage pipelined adder. This adder is operated at 1.67GHz clock frequency in a standard 0.25um CMOS technology with 2.5 V supply voltage.
Keywords
adder; pipeline; carry-select;
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