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A Dual band CMOS Voltage Controlled Oscillator of an arithmetic functionality with a 50% duty cycle buffer  

한윤철 (삼성전자 System LSI 사업부)
김광일 (인하대학교 전자전기공학부)
이상철 (인하대학교 전자전기공학부)
변기영 (인하대학교 UWB-IT 연구센터)
윤광섭 (인하대학교 UWB-IT 연구센터)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.41, no.10, 2004 , pp. 79-86 More about this Journal
Abstract
This paper proposes a dual band Voltage Controlled Oscillator(VCO) with a standard 0.3${\mu}{\textrm}{m}$ CMOS process to generate 1.07GHz and 2.07GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder(HA) was capable of producing a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561MHz/V and 14.6mW, respectively. The phase noises of the dual band VCO are measured to be -102.55dBc/Hz and -95.88dBc/Hz at 2MHz offset from 1.07GHz and 2.07GHz, respectively.
Keywords
VCO; Duty cycle buffer; HA;
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