A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

To handle the density increase of SRAMs, a new parallel testing methodology based on built-in self test (BIST) is developed, which allows to access multiple cells simultaneously. The main idea is that a march algorithm is dperformed concurently in each baisc marching block hwich makes up whole memory cell array. The new parallel access method is very efficient in speed and reuqires a very thny hardware overhead for BIST circuitry. Results show that the fault coverage of the applied march algorithm can be achieved with a lower complexity order. This new paralle testing algorithm tests an .root.n *.root.n SRAM which consists of .root.k * .root.k basic marching blocks in O(5*.root.k*(.root.k+.root.k)) test sequence.

In this paper, we propose a memory compiler to genrate embedded RAMs and ROMs for ASIC chips. We design the leaf cells to be compsoed of memory blocks. The compiler is built using tile-based method to simplify routing. The compiler can genrate any memory layouts to satisfy 64 to 4096 words and 4 to 256 bits per word. The technology we used here is 0.8.mu.m single poly double metal CMOS process. The address access time and power consumption are verifie dthrough the HSPICE simulation.

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.

An 8th-order elliptic low-pass filter with cutoff frequency of 3.13kHz is presented. The design procedure is based on teh 1/s impedance transformation which is applied to a minimum capacitor LC ladder network.The tranformed network is implemented with resistors and high Q frequency-dependent negative resistors (FDNR's). The high Q FDNR is realized with two transadmittance amplifiers. Detailed SPICE simulations show that the iflter has pass-band ripple of 0.18dB, stop-band attenuation over 100dB, cutoff frequency of 3.13 khz, and cutoff frequency temperature coefficient of 8.5ppm/.deg. C at supply voltage of .+-.5V.

New types of PFD (phase-frequency detector) are proposed with reset time and propagation delay reduced. The perfomrance of our proposed PFDs are confirmed by SPICE simulation with 0.8.mu.m CMOS process parameter. As a result of simulation, the reset time of PFDs are 0.32 nsec and 0.030 nsec in capture-process. The proposed PFDs can be used in hihg-speed phase-licked loop (PLL).

We studied the effects of fractional fourier transform in face recognition, in which only the amplitude spectra of transformed facial images were used.We used two recently developed face recognition methods, the most effective feature (MEF) method (i.e., eigenface method) and most discriminating feature (MDF) method, and the effects of th etransform for th etwo methods were consistent. We confirmed that the recognition rate by the use of MDF method is better than that consistent. We confirmed that the recognition rate by the use of MDF method is better than that by MEF regardless of the order to transform, these methods provided slightly better results when the order was 1 than for any other order values. Only when the order was close to 1, the recognition rates were robust to the shift of the input images, and the trend that the recognition rates decreased as the input size varied was independent of the order. From these results, we fond that it is most advantageous to use the amplitude spectra of the conventional fourier transform whose order is 1.

The neural network predictiv econtroller (NNPC) is proposed for the attempt to mimic the function of brain that forecasts the future. It consists of two loops, one is for the prediction of output (NNP:neural network predictor) and the other one is for control the plant(NNC: neural network controller). The output of NNC makes the control input of plant, which is followed by the variation of both plant error and predictin error. The NNP forecasts the future output based upon the current control input and the estimated control output. The input and the output data of a system and a new method using evolution strategy are used to train the NNP. A two-step NNPC is applied to control the temeprature in boiler systems. It was compared with PI controller and auto-tuning PID controller. The computer simulaton and experimental results show that the proposed method has better performances than the other method.