VHDL simulation requires both analysis and elaboration processes. Reducing the time taken by these processes shorten design cycles. We propose an incremental analysis and elaboration algorithm for VHDL, which minimizes the number of design units to be re-analyzed and re-elaborated after an incremental change, thereby reducing the desing cycle time. Experimental results show about four times performance improvement in analysis and 1.25 times in elaboration over the conventional method.

This paper proposes a routing model based on the HVHD for four-layer routing problems. Differing from the HVHV and HVHH models, the proposed HVHD model permits diagonal routing on the fourth laye rwith a grid of 45.deg., 90.deg. and 135.deg. directions. The developed algorithm which uses a channel-graph including weights routes a layer using diagonal model and the othe rthree layers using HVH model. Applications to several benchmark examples verify that approximately 10~25 percent reduction of channel density can be achieved compared to the conventional four-layer channel routing algorithms.

A CMOS 950 MHz frequency synthesizer is designed and fabricated in a 0.8.mu.m standard CMOS process for IS-95-A CDMA mobile communication transceivers To utilize a CMOS ring VCO in a CDMA wireless communication receisver, we employed a QDC (quasi-direct conversion) receiver architecture for CDMA applications. Realized RF frequency synthesizer used as the RF local oscillator for a QDC receiver exhibits a phase noise of -92 dBc/Hz at 885kHz offset from the 950.4 MHz carrier, which complies with IS-95-A CDMA specification. It has a rms jitter of 23.7 ps, and draws 30mA from a 5V supply. Measured I/Q phase error of the 950.4 output signals is 0.7 degree.

In this paper, we designed a motion estimator for MPEG-2 video coder using VHDL. Motion estimation is indispensable for encoding MPEG 2 video. Motion estimation takes over 50% computation power of video encoding 37 frames per second and is suitable for real-time processing. The number of data accesses for computation is fewer than 2 times compared with that of old one. This makes slower memory module available. We minimize input pins to migrate input data through PEs. This processor can compute various motio estimation modes at one calculation that is supported by MPEG-2 video standard. Also independent control architecture makes this processor a single processor or a sub module in amultimedia chip.

This paper concerns a VHDL design and simulation of an accurate and cost-effective fuzzy logic controller (FLC). The accurcy of the proposed FLC is obtained by using the center of gravity (COG) defuzzifier that considers both membership values and spans of membership functions in calculating a crisp value. The cost-effectiveness of the proposed FLC is obtained by restructuring the conventional FLC in the following ways: Firstly, the MAX-MIN inference is inference is replaced by a read-modify-write operation that can be implemented economically in the structure of register files. Secondly, the division in the COG defuzzifier is avoided by finding the moment equilibrium point. The proposed COG defuzzifier has two disadvantages that it requires additional multipliers and it takes a lot of computation time to find the moment equilibrium point. The first disadvantage is overcome by replacing the mulitpliers with stochastic AND operations and the second disadvantage is alleviated by using a coarse-to-fine searching algorithm. The proposed FLC is described in VHDL structurally and behaviorally and whether it is working well or not is checked on SYNOPSYS VHDL simulator by using the truck backer-upper control problem.

Prototype based methods are commonly used in cluster analysis and the results may be highly dependent on the prototype used. In this paper, we propose a fuzzy clustering method that involves adaptively expanding convex polytopes. Thus, the dependency on the use of prototypes can be eliminated. The proposed method makes it possible to effectively represent an arbitrarily distributed data set without a priori knowledge of the number of clusters in the data set. Specifically, nonlinear membership functions are utilized to determine whether a new cluster is created or which vertex of the cluster should be expanded. For this, the membership function of a new vertex is assigned according to not only a distance measure between an incoming pattern vector and a current vertex, but also the amount how much the current vertex has been modified. Therefore, cluster expansion can be only allowed for one cluster per incoming pattern. Several experimental results are given to show the validity of our mehtod.

With the vigorous researches in the character recognition, the need to recognize run-on multilingual handwritten characters is increasing to provide uses with more comfortable PUI(pen user interface) environments. In general, many intermediate word candidates word candidates are generated in run-on multilingual recognition because there is no information of ending position and linguistic kind of character. To remove unnecessary word candidates which are generated in run-on multilingual recognition, we classify them into two groups and select the best candidate among the word candidates in the group where the final characater is completed using 5 attributes. In this research, we propose a method in order to select the best one candidate. It is called WRM (Weighted ranking method). The weights are adaptively trained by LMS(Least mean square) learning rule. Results show that the abilities of decision makin gusing weights are much better than those not using weights.

In this paper, we propose HMCNN(hybrid multiple component neural networks) that enhance performance of MCNN by adapting new pattern partitioning algorithm which can cluster many input patterns efficiently. Added neural network performs similar learning procedure that of kohonen network. But it dynamically determine it's number of output neurons using algorithms that decide self-organized number of clusters and patterns in a cluster. The proposed network can effectively be applied to problems of large data as well as huge networks size. As a sresutl, proposed pattern partitioning network can enhance performance results and solve weakness of MCNN like generalization capability. In addition, we can get more fast speed by performing parallel learning than that of other supervised learning networks.

In this paper, we analyze the dynamics of langevine competitive learning neural network based on its fokker-plank equation. From the viewpont of the stochastic differential equation (SDE), langevine competitive learning equation is one of langevine stochastic differential equation and has the diffusin equation on the topological space (.ohm., F, P) with probability measure. We derive the fokker-plank equation from the proposed algorithm and prove by introducing a infinitestimal operator for markov semigroups, that the weight vector in the particular simplex can converge to the globally optimal point under the condition of some convex or pseudo-convex performance measure function. Experimental resutls for pattern recognition of the remote sensing data indicate the superiority of langevine competitive learning neural network in comparison to the conventional competitive learning neural network.

In this paper, we design andimplement a prototype of the distant ITS (Intelligent tutoring system): English tutor which is running on the information superhighway. It is designed for the purpose of teaching the english conversation effectively to the students whose mother tongues are not english. The tutor could chosse appropriate tutoring strategies and teach the students effectively according to the contents of the student model. And also it is based on the remote data management client/Server model and implemented on SPARC station and pentium PC using oracle 7.3 and power Builder 5.0.