This paper proposes GaN film as a piezoelectric material for SAW(surface acoustic wave) filters. The fabricated GaN SAW filter exhibited a very high velocity of 5800 ㎧and relatively low insertion loss of -9.9 dB without matching circuit. From Smith's equivalent circuit model, the calculated electromechanical coupling factor (K$^2$) was about 4.$\pm$03％. which is larger than those obtained from other thin film piezoelectric materials and allows the realization of wider filter fractional bandwidths.

To increase the device linearities and the breakdown-voltages of FETs, Al$\sub$0.25/ Ga$\sub$0.75/AS / In$\sub$0.25/Ga$\sub$0.75/As / Partially doped channel FET(DCFET) structures are proposed. The metal- insulator -semiconductor (MIS) like structures show the high gate-drain breakdown voltage(-20 V) and high linearities. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range.

In this paper, we have fabricated the PHEMT's with AlGaAs/InGaAs/GaAs and measured characteristics of DC and frequencies. The PHEMT's has a 0.35$\mu\textrm{m}$ gate length, gate width of 60$\mu\textrm{m}$ and 80$\mu\textrm{m}$, and fingers of 2 and 4. From the measurements results for the 60$\mu\textrm{m}$ ${\times}$ 2 PHEMT's, we obtained 1.2V of Vk, -3.5V of Vp, 46mA of Idss, 221mS/mmof gm, and 3.6dB of S$\sub$21/ gain, 45GHz of f$\sub$T,/ 100GHz of fmax. And, in case of 80$\mu\textrm{m}$ ${\times}$ 4 PHEMT's, we obtained 1.2V of Vk, -4.5V of Vp, 125mA of Idss, 198mS/mm of gm, and 2.0dB of S$\sub$21/ gain. 44GHz of f$\sub$T/, 70GHz of fmax at 35GHz frequency. Also, MAG are decreased as a number of finger are Increased.

DC and low frequency noise characteristics of InGaP/InGaAs pseudomorphic HEMTs (p-HEMTs) grown by compound source MBE are investigated for temperature range of 150K to 370K. Equivalent input noise spectra( $S_{iv}$ ) were measured as a function of frequency and temperature. $S_{iv}$ was measured to be 3.4 $\times$ 10$^{-12}$ $V^2$/ Hz at 1kHz for 1.3 X 50${\mu}{\textrm}{m}$$^2$InGaP/InGaAs p-HEMT at room temperature. Measurements of the low-frequency noise spectra of the p-HEMT as a function of temperature show that the trap with an activation energy level around 0.589 eV is a dominant trap that accounts for the low-frequency noise behavior of the device. The normalized extrinsic gm frequency dispersion of the p-HEMT. was as low as 2.5％ at room temperature, indicating that the device has well-behaved low-frequency noise characteristics. Sub-micron (0.25 $\times$ 50${\mu}{\textrm}{m}$$^2$) gate p-HEMT showed $f_{T}$ and $f_{max}$ of 40GHz and 108GHz, respectively.y.y.

We have investigated a process for the preparation of high-quality tantalum oxynitride ( $T_{a}$ $O_{x}$ $N_{y}$) via the N $H_3$ annealing of 7$_{a2}$ $O_{5}$, for use in gate dielectric applications. Compared with tantalum oxide (7$_{a2}$ $O_{5}$), a significant improvement in the dielectric constant was obtained by the N $H_3$ treatment. In addition, light reoxidation in a wet ambient at 45$0^{\circ}C$ resulted in a significantly reduced leakage current. We confirmed nitrogen incorporation in the tantalum oxynitride ( $T_{a}$ $O_{x}$ $N_{y}$ by Auger Electron Spectroscopy. By optimizing the nitridation and reoxidation process, we obtained an equivalent oxide thickness as thin as 1.6nm and a leakage current of less than 10mA/$\textrm{cm}^2$ at 1.5V..5V..5V..5V..5V..5V.

Ferroelectric P $b_{0.99}$〔(Z $r_{0.6}$S $n_{0.4}$)$_{0.9}$ $Ti_{0.1}$〕$_{0.98}$N $b_{0.02}$ $O_3$(PNZST) thin films were deposited by a RF magnetron sputtering on (L $a_{0.5}$S $r_{0.5}$)Co $O_3$(LSCO)/Pt/Ti/ $SiO_2$/Si substrate using a PNZST target with excess PbO of 10 mole％. The thin films deposited at the substrate temperature of 500 $^{\circ}C$ were crystallized to a perovskite phase after rapid thermal annealing(RTA) The thin films annealed at 650 $^{\circ}C$ for 10 seconds in air exhibited the good crystal structures and ferroelectric properties. The remanent polarization and coercive field of the PNZST capacitor were about 20 $\mu$C/$\textrm{cm}^2$ and 50 kV/cm, respectively. The reduction of the polarization after 2.2$\times$10$^{9}$ switching cycles was less than 10 ％.0 ％.％.0 ％.0 ％.

In this paper, the effects of La addition of PLZT(x/30/70) thin films Prepared by sol-gel method are investigated for NVFRAM application. The tetragonality (c/a), the grain size, and the surface roughness of PLZT thin films decrease with an increase of La concentration. As the La concentration increases, the dielectric constants at 10 kHz increase from 450 to 600, while the loss tangent decrease from 0.075 to 0.025. Also, the leakage current density at 100kV/cm decrease from 5.83$\times$10$^{-7}$ to 1.38$\times$10$^{-7}$ 4/$\textrm{cm}^2$. In the results of hysteresis loops measured at $\pm$170kV/cm, the remanent polarization and the coercive field of PLZT thin films with La concentration from 0 to 10㏖％ decrease from 20.8 to 10.5 $\mu$C/cm and from 54.48 to 32.12kV/cm, respectively. After a fatigue measurement by applying 10$^{9}$ square pulses with $\pm$5V, the remanent polarizations of PLZT thin films with 0 and 10㏖％ La concentration decrease about 64 and 42 ％ from initial state. In the results of retention measurement after 10$^{5}$ s, PLZT thin films with 0 to 10mo1％ La concentration show that the remanent polarization is decreased about 43％ and 9％ from initial state, respectively.

Oxide-nitride-oxide(ONO) structures were formed by sequential radio frequency reactive magnetron sputtering method. The chemical composition and structure of these films were studied by using of secondary ion mass spectroscopy(SIMS) and Auger electron spectroscopy(AES) SIMS and AES experiments show the existence of nitridation at the SiO$_2$/Si substrate. The electrical characteristics of ONO films were evaluated by I-V and high frequency C-V measurements When the ONO films were annealed at 90$0^{\circ}C$ for 30 sec in $N_2$ ambient, the breakdown voltage increased and flat-band voltage decreased under high electric field.

The adaptive learning circuit is designed the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results is analyzed. The output frequency of the adaptive learning circuit is inversely proportioned to the source-drain resistance of MFSFET and the capacitance of the circuit. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of imput pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristics of the adaptive learning circuit, that is, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed.

The electrons and holes trapped in the tunneling oxide and interface-states generated in the Si/SiO$_2$ interface during program/erase (P/E) operations are known to cause reliability problems which can deteriorate the cell performance and cause the V$_{th}$ window close. This deterioration is caused by the accumulation of electrons and holes trapped in the oxide near the drain and source side after each P/E cycle. we propose three new erase schemes to improve the cell's endurance characteristics: (1)adding a Reverse soft program cycle after the source erase operation, (2)adding a detrapping cycle after the source erase operation, (3)adding a convergence cycle after the source erase operation. (3) is the most effective performance among the three erase schemes have been implemented and shown to significantly reduce the V$_{th}$ window close problem. And we are able to design the reliable periperal circuit of flash memory by using the (3).(3).

본 연구는 α-Si:H TFT(Amorphous Silicon Thin Film Transistor)를 대체 할 펜타센을 활성층으로 사용하는 박막 트랜지스터를 제작에 관한 것이다. 유기 박막 트랜지스터는 유기발광소자와 함께 유연한 디스플레이에 응용된다. 펜타센 박막 트랜지스터의 제작은 채널 길이 25㎛, 70㎛, 소스, 드레인, 게이트 전극으로 Au을 lift off 공정으로 제작하였으며, 펜타센은 OMBD(Organic Molecular Beam Deposition)로 기판온도를 80℃로 유지하여 증착하였다. 제작된 소자로부터 트랜지스터 전류-전압 특성곡선을 측정하였고, 게이트에 의한 채널의 전도도가 조절됨을 확인하였다. 그리고, 전달특성곡선으로부터 문턱전압과 전계효과 이동도를 추출하였다.

플라즈마 디스플레이 패널의 발광효율을 개선하기 위하여 sustain 구간의 파형을 변화시킨 새로운 구동파 형을 제안하였다. 제안된 sustain 파형은 기존의 구형파에 기울기를 가진 ramp 형태의 파형을 덧붙여 줌으로써 Self-Erasing을 유도하는 파형이다. 기존에 제안된 Self-Erasing을 이용한 구동방식은 높은 구동주파수(>150kHz)에서만 발광효율이 개선되는 반면, 본 논문에서 제안하는 파형은 낮은 구동주파수(25kHz)에서도 30％정도의 발광효율이 개선되었다. 본 논문의 결과로부터 주파수, 듀티, 기울기 등의 다양한 구동조건에서의 연구가 진행된다면 더 큰 발광효율개선이 기대된다.

The temperature effects of programming speed and endurance characteristics in p-channel flash memory cell have been investigated. In the case of room temperature, the programming speed of p-channel flash memory by using BTB scheme is faster than that by using CHE scheme. However, endurance characteristics with BTB programming scheme is not better than that with CHE programming scheme. In the case of elevated temperature, CHE programming speed is reduced due the gate current degradation but BTB programming speed is enhanced due to the increasing of gate current. Finally, the endurance characteristics of both schemes are improved due to the reduction of gate oxide traps.

In this paper, we have made a comparison between secondary ion mass spectroscopy(SIMS) data by the 5kcV-15keV boron implantation and computer simulation results. In order to make electrical activation of implanted carriers, thermal annealing are carried out by RTP method for 30s at 1000$^{\circ}C$ Two dimensional doping concentration distribution from different mask dimensions under inert gas annealing, dry-, and wet-oxidation condition were calculated and simulated with microtec simulator.

We have investigated the relationship between electrical and morphological properties of titanium silicide films. In this study, the C54 titanium silicides were formed by using high temperature sputtering and one-step annealing. From the measurement of electrical and morphological properties, a smooth surface and a relaxed roughness were observed for the titanium silicide film fabricated by high temperature sputtering. And it seems that the previous effect could improve electrical properties.

Tungsten silicide(WSi$_2$) is proposed for the alternate gate electrode of ULSI MOS devices. Good structural property and low resistivity of WSi$_2$ deposited by a low pressure chemical vapor deposition(LPCVD) method directly on SiO$_2$ is obtained after annealing. Especially, WSi$_2$-SiO2 interface remains flat after annealing tungsten silicide at high temperature. Electrical characteristics of annealed WSi$_2$-SiO$_2$-Si(MOS) capacitors were improved in view of charge trapping.

In this paper, we have measured the oxygen contents by FTIR in silicon wafer various process technology(slicing, lapping, polishing). The measured data are also compared with the data of etching process(KOH, Bright etching). Also we have measured the surface morpology in backside silicon wafer after etching treatment and etch pit density due to OISF after 4 step high temperature annealing process with optical microscope.

This paper investigates the complex permittivity of foam materials using the rectangular waveguide. The transmission coefficients of materials inserted in the waveguide are measured with a network analyzer and calculated from the equivalent transmission line model. We use the trial and error method in the acquisition of the complex permittivity.

The 3$\mu\textrm{m}$-thick PVDF (Polyvinyiidene fluoride) thin film have been prepared using physical vapor deposition with electric field, and its FT-IR specrum, dielectric property and electric conduction phenomenon have been investigated. Since the characteristic peaks ate detected at 509.45 and 1273.6〔cm〕 in the FT-IR spectrum, we are confirmed that the ${\beta}$ -phase is dominant in the PVDF thin film. In the results of dielectric properties, the PVDF thin film shows anomalous dispersion, i.e. gradual decrease of dielectric constant with increase of frequency, and also that the dielectric absorption point changes from 200Hz to 7000Hz with increasing temperature of thin film, which is consistent with the Debye's theory. The activation energy (ΔH) obtained from temperature dependence of dielectric loss is 21.64 ㎉/㏖. We confirm that the electric conduction mechanism of PVDF thin film is dominated by ionic conduction by investigating the dependence of the leakage current of the thin film on the temperature and the electric field.

본 연구에서는 유기물 전자소자 개발을 위한 기초 연구로서 증착시 기판의 온도, 증칙비, 열처리 온도에 따른 펜타신 박막의 수평방향 전기전도도, 접촉저항, 면저항 둥 전기적 특성을 측정 하였다. 시료는 분말형 펜타신을 유기분자선 성막장치(OMBD)를 이용하여 성막 하였다. 전도도 계산을 위한 두께의 측정은 $\alpha$-step을 이용하였으며, TLM(transfer length method)으로 접촉저항, 면저항등 전기적 특성을 측정하였다. 전극은 Au를 사용하여 진공 증착법으로 제작하였다. 기판의 온도는 3$0^{\circ}C$, 4$0^{\circ}C$, 5$0^{\circ}C$, 6$0^{\circ}C$, 7$0^{\circ}C$, 8$0^{\circ}C$, 10$0^{\circ}C$ 일곱 종류로 하여 증착비를 달리 하였고, 열처리에 의한 효과는 10$0^{\circ}C$에서 증착한 시료를 10$0^{\circ}C$, 14$0^{\circ}C$에서 각각 10초간 열처리를 실시하였다. 기판 온도에 따른 막의 형상은 AFM을 이용하여 관찰하였다. 기판의 온도가 상승할수록 박막의 결정화가 활발히 진행되었으며 최대단일결정은 4$\mu\textrm{m}$였다. 전기전도도는 7.40$\times$$10^{-7}$ S/cm ~ 0.778$\times$$10^{-5}$ S/cm의 값을 나타내었으며, 접족저항은 10$0^{\circ}C$에서 증착하고 14$0^{\circ}C$에서 10초간 열처리 한 경우 2.5324㏁으로 가장 작았으며, 면저항은 약간의 차이는 있으나 전체적으로 ≒ $10^{9}$ Ω/ 의 값을 보였다

In this paper, a high gain-broad bandwidth MMIC distributed amplifier was designed using cascaded single section distributed amplifier configuration. The PHEMT for this studies was fabricated at our lab The PHEMT has a 0.2 $\mu\textrm{m}$ gate length. a 80 $\mu\textrm{m}$ unit gate width and 4 gate fingers. A designed MMIC amplifier have higher S$\sub$21/ gain than the common distributed amplifier using the same number of active devices. From the simulated result, we obtained that the S$\sub$21/ gain of DC ∼ 20 GHz bandwidth was 15.6 dB and flatness was ${\pm}$0.9 dB, and input and output reflection coefficient were lower than -8 dB. The simulated gain shows an improvement 7.3 dB compared with those of conventional distributed amplifier. And the chip size is 2.0 ${\times}$ 1.2 $\textrm{mm}^2$.

An MMIC oscillator operating at the 24.55 GHz has been designed using 0.2 ${\mu}{\textrm}{m}$AlGaAs/InGaAs/GaAs Pseudomorphic HEMT technology. The active device used in the oscillator design has a 0.2 ${\mu}{\textrm}{m}$ gate length PHEMT with 4$\times$80 ${\mu}{\textrm}{m}$ gate width. We obtained 4.08 dB of S$_{21}$ gain and 317 mS/mm of transconductance, and extrapolated unit current gain cut-off frequency (f$_{T}$) and maximum oscillation frequency (fmax) were 62 GHz and 120 GHz, respectively. The circuit are based on a series feedback and negative resistance topology. Microstrip line open stub is used to terminating. The oscillator circuits has designed for delivering maximum power to load and conjugated matching. The simulated small signal negative resistance was 50 Ω. We obtained 1.002 of loop gain and 0.0005$^{\circ}$angle from the simulation by HP libra 6.1. The layout for oscillator is 1.2$\times$1.8 $\textrm{mm}^2$.>.

본 논문에서 항만 자동게이트통관시스템에 사용하기 위하여 단거리전용통신(DSRC)용 OBE에 사용되는 5.8㎓ 송신기 MMIC를 설계하였다. 능동소자로는 GaAs MESFET을 사용하였고, 회로의 복잡도를 줄이기 위해 직접변조방식을 채택하였다. 인접채널간섭의 영향을 줄이기 위하여 드레인 재어 변조회로를 사용하여 -40dBc이하의 인접채널간섭과 70dB 이상의 on/off비를 갖는 5.8㎓ ASK송신기 회로를 설계하였다.

We presents a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and examined electrical parameters with a HP5475A TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3 $\times$ 3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, self inductance 146pH, mutual capacitance 10.9fF and mutual inductance 16.9pH. S parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55㎓ and the loss of 0.26dB. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

The electronic properties of carbon nanotube are currently the focus of considerable interest. In this paper, the electronic properties of finite length effect in carbon nanotube for cabon nanoscale device is presented. To calculate the electronic properties of carbon nanotube, Empirical potential method (Brenner' hydrocarbon potential) for carbon and Tight binding molecular dynamic (TBMD) simulation are used. As a result of study, we have known that the value of the band gap decreases with increasing the length of the tube. The energy band gap of (6, 6) armchair carbon nanotube have the ranges between 0.3 eV and 2.5 eV. Also, our results were compared with the results of the other computational techniques. As that result, our results are very well united.

In this experiment, we fabricated pyramid-type silicon tunneling devices in which a tunneling current flow between a micro-tip and Si$_3$N$_4$ thin film membrane. A MEMS process was used for the fabrication of the tunneling devices. The micro-tips were formed on Si wafers by undercutting a differently oriented square of SiO$_2$ with KOH. The stiffness of the Si$_3$N$_4$ films were observed and the model for the stiffness calculation, which is useful in predicting the stiffness even when the stiffness ranges beyond the scope of the normal experimental condition, was suggested.

Single Electron Transistor Logic (SETL) can be characterized by HSPICE simulation using a SPICE macro model. First, One unit SET is characterized by Monte-carlo simulation and then we fit SPICE macro-modeling equations to its characteristics. Second, using this unit SET, we simulate the transient characteristics of two-input NAND gate in both the static and dynamic logic schemes. The dynamic logic scheme shows more stable operation in terms of logic-swing and on/off current ratio. Also, there is a merit that we can use the SET only as current on-off switch without considering the voltage gain.

Uncooled pyroelectric infrared detectors based on BST(B $a_{-x}$S $r_{x}$Ti $O_3$) thin films have been fabricated by RF magnetron sputtering and surface Micromachining technology. The detectors form BST thin film ferroelectric capacitors grown by RF magnetron sputtering on N/O/N(S $i_3$ $N_4$/ $SiO_2$/S $i_3$ $N_4$) membrane. The sputtered BST thin film exhibits highly c-axis oriented crystal structure that no poling treatment for sensing applications is required. This is an essential factor to increase the yield for realization of an infrared image sensor. surface-Micromachining technology is used to lower the thermal mass of the detector by giving maximum sensor efficiency Gold-black is evaporated on top of the sensing elements used the thermal evaporator. fabricated uncooled pyroelectric infrared detectors is highly output voltage at the low temperature(1$^{\circ}C$).).).

스페클 패턴은 광섬유의 모드 간섭 때문에 발생하는 현상으로, 광섬유에 인가된 미세 외압으로 인해서 발생하는 스페클 패턴의 변화를 이용해 외부압력의 인가여부 및 그 크기를 알 수 있다. 이를 이용하여 본 연구에서는 미세 압력을 외부에서 인가하며 스페클 패턴의 변화에 따른 광 강도의 변화를 측정하였으며, 그 신호는 증폭기와 필터를 거쳐 오실로스코프로 관찰하였다. 그 결과 우리는 이 신호를 관찰하여 부하인가에 대한 응답특성을 실시간에 정확히 확인할 수 있었다. 본 연구에서 제작된 센서는 기존의 센서에 비해 매우 높은 감도를 가지고 넓은 영역을 실시간에 감시할 수 있으며, 저 비용으로 센서를 설계·제작이 가능하므로 범용의 방재용 센서 및 침입 센서에 응용 가능할 것으로 기대된다.

In this paper, we report a new damping circuit with a constant damping rate for RFID applications. The proposed damping circuit is used along with a over-voltage limiter and exhibits almost constant damping rates when the distance between the reader and the transponder varies. This results in keeping the power supply voltage of the transponder constant and in improved reading distances.

In this paper, a 1.8㎓ low noise amplifier was designed and simulated using 0.2$\mu\textrm{m}$ Si CMOS process. Noise characteristics and s parameters were extracted for the 300$\mu\textrm{m}$ gate width and 0.25$\mu\textrm{m}$ gate length NMOS transistors. For high available power gain, each stage was designed cascode type. It revealed available power gain of 23.5dB, noise figure of 2.0dB, power consumption of 15㎽ at 2.5V. It was shown that designed low noise amplifier had good RF performance. Designed Si CMOS LNA is expected to be used for RF front-end in transceiver.

A new Op-Amp output buffer is presented for driving large-size LCD panels. The proposed Op-Amp is designed by combining a common source and a common drain amplifier to have a high slew rate and to minimize the quiescent current. The proposed circuits are simulated in a high-voltage 0.6${\mu}{\textrm}{m}$ CMOS process, dissipates only 20${\mu}{\textrm}{m}$ static current, and have 83dB open-loop DC gain and 60$^{\circ}$phase margin.

In this paper, we have proposed an efficient test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph(STG)〔1〕 which is a kind of specification method for asynchronous circuits. To conduct a high-level test generation, we have defined a high-level fault model, called single State Transition Fault(STF) model on STG and proposed a test generation algorithm for STF model. The effectiveness of the proposed fault model and its test generation algorithm is shown by experimental results on a set of benchmarks given in the form of STG. Experimental results show that the generated test for the proposed fault model achieves high fault coverage over single input stuck-at fault model with low cost. We have also proposed extended STF model with additional gate-level information to achieve higher fault coverage in cost of longer execution time.

In this paper, a new parallel array structure for the asynchronous array multiplier is introduced. This structure is designed for a data dependent asynchronous multiplier to reduces power which is wasted in conventional array structure. Simulation shows that this structure saves 30％ of power and 55％ of computation time comparing to conventional booth encoded array multiplier.

A 16bit asynchronous multiplier has been designed using micropipelind structure with 2 phase and data bundling. And 4-radix modified Booth algorithm, CPlatch(Cature-Pass latch) and modified 4-2 counters have adopted in this design. It is implemented in 0.65$\mu\textrm{m}$ double-poly/double-metal CMOS technology by using 12,074 transistors with core size of 1.4${\times}$1.8$\textrm{mm}^2$. And our design results in a computation rate 55MHz a supply voltage of 3.3V.

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles.

본 논문은 SystemC의 특징과 어떻게 SOC 설계 방법에 응용될 수 있는지 고려한다. 먼저, 기존 개발된 시스템 알고리듬을 기초로 하여 SystemC로 기능 블럭과 인터페이스를 분리하여 정의한다 이렇게 정의된 기능 블록과 인터페이스를 모듈화하고 묶어서 실행 가능한 사양을 만들어 충분한 기능 검증을 수행한다. 두번째로 S/W로 구현할 부분과 H/W로 구현할 부분을 나누어, S/W 부분의 인터페이스는 사이클 정확도를 갖도록 기술하며 기능 블럭은 기존 S/W 개발 환경을 사용하여 구현한다 H/W 부분의 IO 는 다양한 추상화단계로 이벤트를 기술하고 내부 동작은 기능에 기반을 두고 작성한다. 이 사양이 만족해야 할 시스템 요구 성능을 발휘하도록 성능분석을 수행하고, 이 결과가 S/W, H/W 분할 과정과 인터페이스 구체화 과정에 영향을 미친다. 시스템 성능을 내는 이 사양을 기초로 하여 사이클 정확도를 갖는 H/W 부분은 변환 프로그램을 이용하거나 직접 HDL RTL 설계로 변환한다. 이 방법은 기존 C/C++ 프로그램 개발자와 VHDL/Verilog 설계자가 쉽게 적응할 수 있어 기존 ASIC 개발자가 저렴한 비용으로 시스템 통합 설계 및 검증을 통하여 SoC를 개발하고자 할 때 특히 더 적합하다.

본 논문에서는 DVCR용 2-4-8 DCT core의 VSIA(Virtual Socket Interface Allience) 2.2 compliant IP의 구현에 대하여 기술한다. 본 논문에서 기술한 2-4-8 DCT/IDCT core는 Soft IP이며, VSIA의 deliverable document ver. 2.2에서 정의한 Soft-IP에 대한 72가지의 필수 항목, 조건부 필수 항목, 권고 항목 등의 전달물을 각 DWG(Development Working Group)의 사양에서 정의하고 있는 규격에 맞추어 가공하였다. 또한 본 논문에서는 Soft-IP에 대한 VSIA 권고안 및 VSIA deliverable list에 대하여 기술하고, VSIA compliant IP화를 위한 방법에 대하여 설명하였다.

The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

A hardware architecture to implement the SEED block cipher algorithm into one chip is described. Each functional unit is designed with VHDL hardware description language and synthesis tools. The designed hardware receives a 128-bit block of plain text input and a 128-bit key, and generates a 128-bit cipher block after 16-round operations after 8 clocks. The encryption time is within 20 nsec.

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

Silicon semiconductor technology agree that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduce verification time. This Paper describe the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

This paper proposes the optimized hardware architecture for a high performance image downscaler The proposed downscaler uses non-linear digital filters for horizontal and vertical scalings. In order to achieve the optimization, the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The performance of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using the VHDL and implemented by using the IDEC-C632 0.65$\mu\textrm{m}$ cell library.

In this paper, we described a design of the input buffer system for efficiently dealing with MPEG audio bitstream to demux header and side information, audio data. In order to overcome the limitations of fixed-word manipulation in bitstream demuxing, we proposed a new variable length bit retrieval system with FSM sequencer supporting MPEG audio frame format, and serial buffer demuxing audio stream, FIFO circular buffer including header and side information.

In this paper, we propose the novel test method to detect short and open faults in CMOS Op-amp. The proposed method is composed of two test steps - the offset and the high frequency test. Using HSPICE simulation, we get a 100％ fault coverage. To verify the proposed method, we design and fabricate the CMOS op-amp that contains various short and open faults through Hyundai 0.65$\mu\textrm{m}$ 2-poly 2-metal CMOS process. Experimental results of fabricated chip demonstrate that the proposed test method can detect short and open faults in CMOS Op-amp.

In this work, I propose a temperature stable voltage-to-frequency converter in which the output frequency is directly proportional to the input voltage. The output frequency range is from 20㎑ to 60㎑ and the difference between simulated and calculated values is less than about 5％ for this range of output frequency. The temperature variation of sample output frequencies is less than ${\pm}$0.5％ in the temperature range -25$^{\circ}C$ to 75$^{\circ}C$.

This paper proposes a CMOS low noise VGA. It describes the noise optimization method of the proposed VGA. The designed VGA provides of a 0 to 21.30dB gain variation and its bandwidth of 49MHz. The input reflected noise voltage is 4.84nV/sqrt-hz at 1MHz and noise figure is 14.53dB(Rs=50 Ω). The VGA was fabricated using a 0.35-${\mu}{\textrm}{m}$ CMOS technology.

In this paper, an A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s. This architecture is proposed using the 2-step architecture for high speed conversion rate. It is consisted of sample/hold circuit, low power comparator, voltage reference circuit and DAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.2$\mu\textrm{m}$ CMOS technology. The SNR is 45.3dB at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}$1 / ${\pm}$2 LSB, respectively. The power consumption is 13㎽ at single +2.5V supply voltage.

In this paper, a low voltage CMOS analog four-quadrant multiplier using two V-I converters is presented. The proposed V-I converter is composed of the series composite transistor and the low voltage composite transistor. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25$\mu\textrm{m}$ n-well CMOS process parameters with a 2V supply voltage. Simulation results show that the power dissipation is 1.55㎿, the cutoff frequency is 489MHz, and the THD can be 0.26％ at maximum differential input of 1V$\sub$p-p/.

Charge pump based upon a phase locked loop(PLL) is described. This charge pump show that it is possible to overcome the issue of charge pump current mismatch by using a current subtraction circuit. Also, this charge pump can suppress reference spurs and disturbance of the VCO control voltage. HSPICE simulations are performed using 0.25$\mu\textrm{m}$ CMOS process.

Minimum-cost linear network flow problems could be transformed with equal to assignment problems. Traditional method to solve the linear network flow problems are improved source-cost by transform the simple cycle flow. Auction algorithm could be applied to same element using the initial target price and dispersion calculation. Also, each elements are obtained by $\varepsilon$-relaxation methods. In this paper we proposed; 1)minimum-cost flow problem, 2)minimum-cost flow problem by the mathematical equivalent and 3) extraction $\varepsilon$-relaxation & expand transfer problem with minimum-cost flow. It can be applicant to PCB design by above mentioned.

In this paper, A low-power MOS monolithic peak detector is presented. Designed for monolithic and low-power characteristics, this MOS peak detector can be integrated easily on the same chip as a module of large communication systems. The simulation results of this peak detector which was composed with four NMOSs and two capacitors show the power dissipation of 0.972㎽ and the good operations for 2㎓ operating pulse frequency. Therefore, it may be used as a functional block for various signal processing systems.

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

A parallel concatenated convolutional coding scheme consists of two constituent systematic convolutional encoders linked by an interleaver. The information bits at the input of the first encoder are scrambled by the interleaver before entering the second encoder.〔1〕-〔3〕Now many different interleavers are presented for Turbo code. The topic of this paper is to design of the interleaver which is for IS-2000 Turbo code.

In this paper, a method to implement new Quasi-SOI LDMOSFET is introduced and the electrical characteristics of the device are studied. Key process steps of the device are explained briefly. By performing process and device simulations, electrical characteristics of the device are investigated, with emphasis on the optimization of the tilt angle of p$\^$0/ channel region. The electrical properties of the Quasi-SOI device are compared with those of bulk and SOI devices with the same process parameters. Simulated device characteristics are threshold voltage, off-state leakage current, subthreshold swing, DIBL, output resistance, lattice temperature, I$\_$D/-V$\_$Ds/, and cut-off frequency.

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA. (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL models. We have peformed logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5 $\mu\textrm{m}$ standard cell library (STD80). The total number of gates is about 130,000.

In this paper we present new idea to highly compress the images. The previous image is transformed with wavelet and the transformed data are transmitted. The previous image is subtracted from the next image. Then difference values per pixel are scanned to search motion areas and boundaries. In the motion boundaries, motion vectors and error values are transformed with wavelet and transmitted. We also include camera motion estimation and compensation. In this method this system has advantages of more compressive data, better quality of picture and shorter processing time compared to MPEG2, MPEG4.

In this paper, we describe an automated extraction program that transforms a mask layout into an approximated equivalent circuit information suitable for circuit simulation, and that extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. To extract equivalent circuit from mask layout, we propose new block disassembly technique capable of accurate computations of distributed RCs at branch point, using vectorized edges which represent the outline of an individual polygon.

In this paper, we Implement a new arithmetic computation for MPEG audio data to overcome the limitations of real number processing in the fixed-point arithmetics, such as: overheads in processing time and power consumption. We aims at efficiently dealing with real numbers by extending the fixed-point arithmetic manipulation for floating-point numbers in MPEG audio data, and implementing the DSP libraries to support the manipulation and computation of real numbers with the fixed-point resources.

In this paper, we propose a structure of the modified AAL. The ATM adaptation layer(AAL) is described in HDL and implemented in FPGA, which plays a role in receiving of HDTV TS packets over ATM networks. Also We designed the PCI interface module which is used for monitoring and analyzing the HDTV TS packets. The designed FPGA chip operates at 20 MHz.

In this paper, the design of Binary FSK Using Cellular Oscillator Network architecture is newly introduced and analyzed. With its easy frequency controllability and MHz range of quadrature signals, the Cellular Oscillator Network can be used in RF communication systems. Binary Frequency Shift Keying can also be implemented through digital loop-path switching. This FSK model is simulated and proved with typical 3V, 0.5$\mu\textrm{m}$ CMOS N-well process parameters.

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

We have fabricated and analyzed photodiodes for optical link with Si pin structures. As the results of experiment, the web patterned photodiode(type C) with $p^{+}$-guard ring showed low junction capacitance of 6~7 pF at $V_{R}$=-5V and high separation ability for optical signal(dark current : $\leq$ 5 nA, optical signal current : $\geq$ 340 nA) due to the small effective $p^{+}$-n junction area and the expanded electric field region. The fabricated Si pin photodiode can be applicable for detecting an optical signal with the wavelength of about 660~670 nm. It can also be integrated with the twin well CMOS structure to develope an one chip based optical receiver IC. IC.C.

Thin Film Transistor(TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature(500$^{\circ}C$) Metal-Induced Lateral Crystallization(MILC) furnace annealing and high -temperature (700$^{\circ}C$) rapid thermal annealing leads to the improvement of the material quality The TFTs measured with this two-step annealing material exhibit better characteristics than those obtained by using conventional MILC furnace annealing.

In this study, the electrical characteristics of 100V -Class LDMOSFET for high temperature applications such as electronic control systems of automobiles and motor driver were investigated. Measurement data are taken over wide range of temperature(300K-500K) and various drift region length(6.6$\mu\textrm{m}$-12.6$\mu\textrm{m}$). In high temperature condition(>450K), drain current decreased over 50％, and specific on-resistance increased about twice in comparison with room temperature. Moreover the ratio R$\sub$on//BV, a figure of merit of the device, increased with increasing temperature.

Four helical resonators are distributed in a 2 ${\times}$ 2 array by modifying upper part of the conventional reactive ion etching(RIE) type LCD etcher in order to prepare a large area plasma source. Since the resonance condition of the RF signal to the helical antenna, one RF power supply is used for delivering the power efficiently to all four helical resonators without an impedance matching network Previous work of 2 ${\times}$ 2array inductively coupled plasma(ICP)requires one matching circuit to each ICP antenna for more efficient power deliverly Distributions of ion density and electron temperature are measured in terms of chamber pressure, gas flow rate and RF power . By adjusting the power distribution among the four helical resonator units, argon plasma density of higher than 10$\^$17/㎥ with the uniformity of better than 7％ can be obtained in the 620 ${\times}$ 620$\textrm{mm}^2$ chamber.

PHEMT's with three different doping structures, -SH(single-heterojunction), DH (double-heterojunction), and DC(doped-channel)-,were designed, fabricated and characterized to study the effect of doping layer structures on the performance of millimeter-wave PHEMT's. 0.25${\mu}{\textrm}{m}$ DH-PHEMT with below-channel doping of 1$\times$10$^{12}$ c $m^{-2}$ was superior to SH-PHEMT by 40％ in $I_{dss}$, 20％ in f/sib T/ and showed broador gm- $I_{D}$ characteristics which is advantageous to power applications DH-PHEMT showed similar DC and small-signal performance compared with DC-PHEMT. Taking the much higher carrier mobility into considerations, DH-PHEMT is believed to be the best candidate for millimeter-wave, low-noise and/or power applications.s.s.

Low frequency(<100Hz) weak magnetic field(<20gauss) is applied axially to an inductively coupled oxygen plasma(ICP), and its plasma characteristics are monitored by OES(Optical Emission Spectroscopy) and Langmuir probe. It is found that periodic magnetic field enhances ashing rate by 25％ and improves its uniformity upto 4.5％ over 8" wafer. From electron energy distribution function, both low and high energy electrons are identified and relative abundancy is found to be controlled by the applied frequency. Moreover, it is observed that ionization and dissociation species are varied with applied frequency. We insert an aluminium baffle in the chamber to get better uniformity and less plasma damage.

Boron Phosphide films were deposited on the glass substrate at low temperature, 550$^{\circ}C$, by the reaction of B$_2$H$\sub$6/ with PH$_3$ using CVD. N$_2$ was employed as carrier gas. The deposition rate was 1000${\AA}$/min and the refractive index of film was 2.6. The data of XRD show that the film has the preferred orientation of (1 0 1). The VIS spectrophotometer's data proved that the films are transparent in the visible range. Also, we performed AFM, FT-IR measurement. To investigate the annealing effect, the samples were annealed for 1hour, 3hours at 550$^{\circ}C$ and tested.

We investigated the etch rate of SiO$_2$ in E-ICP, ICP system and the addition gas (O$_2$H$_2$) effect on SiO$_2$ etch characteristics. In all conditions, E-ICP shows higher etch rate than ICP. Small amount of O$_2$ addition increase F atom and O$\^$*/ concentration. at optimized condition (30％ O$_2$ in CF$_4$, 70Hz) E-ICP system shows highest etch rate (about 6000${\AA}$). H$_2$addition in CF$_4$ Plasma make abrupt decrease Si etch rate and moderate decrease SiO$_2$ etch rate.

It is important to control the electron energy distribution to have high quality plasma process. A conventional inductively coupled plasma(ICP) source with 13.56MHz power is not adequate for low damage sub-half micron patterning process due to higher electron temperature. Only the pulsed plasma technique seems to provide low electron temperature, and thus low process damage. Recently, a novel method proposed by us, named as ‘Enhanced-ICP’, which uses periodic weak axial magnetic field added to a normal ICP source, has shown great improvement in etch characteristics. changes of plasma characteristics according to the frequency of time-varying axial magnetic field have been observed by probe-time-averaged Langmuir probe.

In this work, we investigated A1 cluster deposition on Al (100) surface using molecular dynamics simulation. A result of simulations showed that large cluster with low energy was proper for good surfaced-films without craters at the low temperatures. We investigated the maximum substrate temperature and the time taken for substrate temperature to reach its maximum as a function of cluster size in the case of the same total energy and in the case of the same energy Per atom. The correlated collisions play an important role in interaction between energetic cluster and surface, and as cluster size and cluster energy increases, the correlated collisions effect affects interaction between energetic cluster and surface.

In this study, the Au/Ni and Au/Ni/Si/Ni layers prepared by electron beam evaporation were used to form ohmic contacts on p-type GaN. Before rapid thermal annealing, the current-voltage(I-V) characteristic of Au/Ni and Au/Ni/Si/Ni contact on p-type GaN film shows non-ohmic behavior. A Specific contact resistance as 3.4$\times$10$^{-4}$ Ω-$\textrm{cm}^2$ was obtained after 45$0^{\circ}C$-RTA. The Schottky barrier height reduction may be attributed to the presence of Ga-Ni and Ga-Au compounds, such as Ga$_4$Ni$_3$, Ga$_4$Ni$_3$, and GaAu$_2$ at the metal - semiconductor interface. The mixing behaviors of both Ni and Au have been studied by using X-ray photoelectron spectroscopy. In addition, X-ray diffraction measurements indicate that the Ni$_3$N, NiGa$_4$, Ni$_2$Si, and Ni$_3$Si$_2$ Compounds were formed at the metal-semiconductor interface.

In order to analyze the characteristics of complicated TFT-LCD (Thin Film Transistor-Liquid Crystal Display) circuits, it is indispensible to use simulation programs. In this study, we present a systematic method of extracting the input parameters of poly-Si TFT for Spice simulation. This method is applied to two different types of poly-Si TFTs fabricated in our group with good results. Among the Spice simulators, Pspice has the graphic user interface feature making the composition of complicated circuits easier. We added successfully a poly-Si TFT model on the Pspice simulator, which would contribute to efficient simulations of poly-Si TFT-LCD pixels and arrays.

We showed that the change of Ar to $N_2$flow during the TiN deposition by the reactive sputtering decides the crystallinity of LPCVD W, as well as the electrical properties of the W-TiN/SiO$_2$Si capacitor. In particular, the threshold voltage can be controlled by the Ar to $N_2$ratio. As compared to the results obtained from the LPCVD W/SiO$_2$/Si MOS capacitor, the insertion of approximately 50 nm TiN film effectively prohibits the fluorine diffusion during the deposition and annealing of W films, resulting in negligible leakage currents at the low electric fields.

N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.

In this paper, a complete methodology of incorporating the displacement current for the calculation of a single electron inverter characteristics has been devised. It has been implemented for the calculation of the low frequency noise spectrum in a single electron inverter in the framework of Monte-Carlo method. Our new methodology opens up a systematic way of analyzing transient behaviors of single electron circuits.

With the recent development of the ultrahigh-speed optical time division multiplexed system, high-repetition rate optical-pulse stream generation is necessary. This is different from conventional approaches, which use fiber or integrated waveguide delay line circuits. The high-repetition-rate optical-pulse multiplication phenomenon occurs when the optical pulse's spectral width is greater than the transfer bandwidth of the coupler used. From the analysis, the output repetition rate can be controlled by using fiber couplers with different equivalent transfer bandwidths. The pulse seperation spacing is controlled by number of cascaded coupler in optical loop mirror coupler scheme.