Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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A novel PLL technique using digital lock-in amplifier under distorted grid conditions

  • Received : 2025.06.13
  • Accepted : 2025.12.07
  • Published : 2026.04.20
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Abstract

IEEE Standards 519 and P1547 enforce strict limits on the harmonics, phase, and frequency variation in grid-connected inverter outputs. Optimally designed phase-locked loops (PLLs) are essential for synchronizing inverters with the grid to satisfy these standards. Various PLL methods have been proposed, but their performances are degraded in the presence of DC offsets and grid harmonics. This paper proposes a novel digital lock-in amplifier PLL (DLA-PLL) to address these challenges. The DLA-PLL utilizes a robust phase-sensitive detector (PSD), making it immune to harmonics and DC offsets except at the fundamental frequency. Simulations and experiments demonstrate the superiority of the proposed DLA-PLL over six conventional PLL methods under highly distorted grid conditions and power-quality events.

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References

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