Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A Study of the Combinatorial Interpolation Algorithm for Scaler Hardware Design

스케일러 하드웨어 설계를 위한 조합 보간 알고리즘의 연구

  • Si-Yeon Han (Dept. of Electronics Engineering, Dong-A University) ;
  • Bong-Soon Kang (Dept. of Electronics Engineering, Dong-A University)
  • Received : 2023.08.31
  • Accepted : 2023.09.24
  • Published : 2023.09.30
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Abstract

As Multimedia industry has evolved, it has become possible to display resolutions in various formats. Therefore, the performance of a scaler algorithm that converts resolutions while maintaining high quality and its hardware implementation are important. Considering the hardware design of an image up/down scaler, this paper proposes a combinatorial scaler algorithm that uses modified bilinear interpolation in the vertical direction and bicubic interpolation in the horizontal direction to reduce the line memory burden. Through quantitative and qualitative evaluations, this paper compared the performance of the proposed algorithm with three other well-known algorithms, and also compared the hardware burden of its hardware implementation. This paper used a sinusoidal signal and eight typical images for performance evaluation.

멀티미디어 산업이 발전함에 따라 다양한 형식의 해상도를 표시할 수 있게 되었다. 따라서 고화질을 유지하며 해상도를 변환하는 스케일러 알고리즘의 성능과 이를 하드웨어로 구현하는 것은 중요하다고 할 수 있다. 본 논문에서는 이미지 확대/축소 스케일러의 하드웨어 설계를 고려하여 수직 방향으로는 수정된 양 선형 보간, 수평 방향으로는 양 3차 회선 보간을 사용하여 라인 메모리 부담을 줄인 조합 스케일러 알고리즘을 제안한다. 본 논문은 정량적 그리고 정성적 평가를 통해 제안하는 알고리즘의 성능을 널리 사용되는 다른 세 가지 알고리즘과 비교 평가하였고, 이를 하드웨어로 구현할 때에 필요한 하드웨어 부담을 비교하였다. 본 논문은 성능평가를 위해 정현파 신호와 8개의 일반 이미지를 사용하였다.

Keywords

Acknowledgement

This paper was supported by research funds from Dong-A University.

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