한국전자통신학회논문지 (The Journal of the Korea institute of electronic communication sciences)

한국전자통신학회 (Korea Institute of Electronic Communication Science)
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m-GDI 압축 회로를 이용한 고성능 곱셈기

High-Performance Multiplier Using Modified m-GDI(: modified Gate-Diffusion Input) Compressor

  • 투고 : 2023.02.21
  • 심사 : 2023.04.17
  • 발행 : 2023.04.30
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초록

압축 회로는 고속 전자 시스템에서 널리 사용되며 곱셈기의 피연산자 수를 감소시키기 위해 사용된다. 본 논문에서 설계한 압축 회로는 m-GDI(: modified Gate-Diffusion Input) 기술을 사용하여 회로의 성능을 향상시켰으며, 4-2, 5-2 및 6-2 압축 회로를 각각 8비트 Dadda 곱셈기 사용하여 성능을 비교하였다. 시뮬레이션 결과, 5-2 압축 회로를 사용한 곱셈기는 4-2 압축 회로와 6-2 압축 회로를 사용한 곱셈기에 비해 전파 지연 시간이 각각 13.99%와 16.26% 감소하였고, PDP(: Power Delay Product)가 각각 4.99%와 28.95% 절감되였다. 하지만 5-2 압축 회로를 사용한 곱셈기는 4-2 압축 회로를 사용한 곱셈기에 비해 소비 전력이 10.46% 증가하였다. 결과적으로 5-2 압축 회로를 사용한 곱셈기가 4-2 및 6-2 압축 회로를 사용한 곱셈기보다 우수한 성능을 갖는 것을 확인하였다. 설계한 회로는 TSMC 65nm CMOS 공정을 사용하여 구현되었으며 SPECTER 시뮬레이션을 통해 그 가능성을 검증하였다.

Compressors are widely used in high-speed electronic systems and are used to reduce the number of operands in multiplier. The proposed compressor is constructed based on the m-GDI(: modified gate diffusion input) to reduce the propagation delay time. This paper is compared the performance of compressors by applying 4-2, 5-2 and 6-2 m-GDI compressors to the multiplier, respectively. As a simulation results, compared to the 8-bit Dadda multiplier using the 4-2 and 6-2 compressor, the multiplier using the 5-2 compressor is reduced propagation delay time 13.99% and 16.26%, respectively. Also, the multiplier using the 5-2 compressor is reduced PDP(: Power Delay Product) 4.99%, 28.95% compared to 4-2 and 6-2 compressor, respectively. However, the multiplier using the 5-2 compression circuit is increased power consumption by 10.46% compared to the multiplier using the 4-2 compression circuit. In conclusion, the 8-bit Dadda multiplier using the 5-2 compressor is superior to the multipliers using the 4-2 and 6-2 compressors. The proposed circuit is implemented using TSMC 65nm CMOS process and its feasibility is verified through SPECTRE simulation.

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과제정보

본 논문은 2022년도 정부(산업통상자원부)의 재원으로 한국산업기술진흥원의 지원을 받아 수행된 연구임(P0017011, 2022년 산업혁신인재성장지원사업)

참고문헌

  1. S. Shubham, C. Hijal, S. Pritam and B. Manoj, "8-bit ALU design using m-GDI technique." 2020 4th International Conference on Trends in Electronics and Informatics, Tirunelveli, India, June 2020, pp. 17-22
  2. A. Shahzad and Y. Kong, "Low-area Wallace multiplier." Vlsi Design vol. 2014, no. 1, Jan. 2014, pp. 1-1.
  3. E. Mohd and K. Achyut, "Design and Verification of 4 X 4 Wallace Tree Multiplier." International Journal of Analytical and Experimental Modal Analysis (IJAEMA) vol. X1, Oct. 2019, pp.657-660.
  4. K. C. Bickerstaff, E. E. Swartzlander and M. J. Schulte, "Analysis of column compression multipliers," In Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15, Vail, CO, USA. Jun 2001, pp. 33-39
  5. A. Morgenshtein, A. Fish and I.A. Wagner, "Gate-diffusion input (GDI)-a technique for low power design of digital circuits: analysis and characterization." 2002 IEEE International symposium on circuits and systems. Proceedings (Cat. No. 02CH37353). Vol. 1. IEEE, 2002.
  6. U. Ramadass and P. Dhavachelvan, "Modified gate diffusion input technique: a new technique for enhancing performance in full adder circuits." Procedia Technology, vol. 6, 2012, pp. 74-81 https://doi.org/10.1016/j.protcy.2012.10.010
  7. G. Nayan, R. K. Prasad, P. K. YG Praveen and Dr. M Z Kurain, "A Review on Modified Gate Diffusion Input Logic: An Approach for Area and Power Efficient Digital System Design." Proceedings of the Second International Conference on Emerging Trends in Science & Technologies For Engineering Systems, Karnataka, India. Jul 2019, pp. 17
  8. A. Morgenshtein, A. Fish and I.A. Wagner, "Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits, 2002 IEEE transactions on very large scale integration (VLSI) systems, vol. 10, no. 5, Oct. 2022, pp.566-581. https://doi.org/10.1109/TVLSI.2002.801578
  9. K. B. Priya and R. Sudarmani, "Performance analysis of Dadda multiplier using 5: 2 compressor and its applications." International Journal of Advanced Information Science and Technology, vol. 5, no. 4, Apr. 2016, pp. 72-78.
  10. R. Ali. "CMOS high-performance 5-2 and 6-2 compressors for high-speed parallel multipliers." Informacije MIDEM, vol. 50, no. 2, 2020, pp. 115-124. https://doi.org/10.33180/InfMIDEM2020.204