전력전자학회논문지 (The Transactions of the Korean Institute of Power Electronics)

  • 제28권1호
  • /
  • Pages.39-47
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  • 2023
  • /
  • 1229-2214(pISSN)
  • /
  • 2288-6281(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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SiC 전력반도체의 병렬 구동 시 전류 불균형을 최소화하는 Mezzanine 구조의 방열일체형 스위칭 모듈 개발

Development of Switching Power Module with Integrated Heat Sink and with Mezzanine Structure that Minimizes Current Imbalance of Parallel SiC Power Semiconductors

  • Jeong-Ho Lee (Dept. of Electrical Engineering, HYPEC-EPECS Lab, Hanyang University) ;
  • Sung-Soo Min (Dept. of Electrical Engineering, HYPEC-EPECS Lab, Hanyang University) ;
  • Gi-Young Lee (Dept. of Electrical Engineering, Gyeongsang National University) ;
  • Rae-Young Kim (Dept. of Electrical Bio-Engineering, Hangyang University)
  • 투고 : 2022.08.26
  • 심사 : 2022.09.26
  • 발행 : 2023.02.20
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초록

This paper applies a structural technique with uniform parallel switch characteristics in gates and power loops to minimize the ringing and current imbalance that occurs when a general discrete package (TO-247)-based power semiconductor device is operated in parallel. Also, this propose a heat sink integrated switching module with heat sink design flexibility and high power density. The developed heat dissipation-integrated switching module verifies the symmetry of the parasitic inductance of the parallel switch through Q3D by ansys and the validity of the structural technique of the parallel switch using the LLC resonant converter experiment operating at a rated capacity of 7.5 kW.

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과제정보

본 논문은 (주)제이알솔루텍 산학협동과제(과제명: 30kW급 연료전지용 DC-DC 컨버터 및 특주품 개발)의 지원을 받아 수행된 연구 결과입니다.

참고문헌

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  3. Y. Wen, Y. Yang and Y. Gao, "Active gate driver for improving current sharing performance of paralleled high-power SiC MOSFET modules," IEEE Transaction on Power Electronics, Vol. 36, No. 2 pp.1491-1505, Feb. 2021.  https://doi.org/10.1109/TPEL.2020.3006071
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  7. C. Zhao, L. Wang, X. Yang, F. Zhang and Y. An, "Comparative investigation on paralleling suitability for SiC MOSFETs and SiC/Si cascode devices," Proc. IEEE Transactions on Industrial Electronics, Vol. 69, pp. 3503-3514, Apr. 2019.  https://doi.org/10.1109/TIE.2021.3070519
  8. S. Yang, J. Soh, S. Min and R. Kim, "Parasitic inductance reduction design method of vertical lattice loop structure for stable driving of GaN HEMT," The Transactions of The Korean Institute of Power Electronics, Vol. 25, No. 3, pp. 195-203, Jun. 2020. https://doi.org/10.6113/TKPE.2020.25.3.195