Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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FPGA Design of a Parallel Canny Edge Detector with Optimized Local Buffers

로컬 버퍼 최적화를 통한 병렬 처리 캐니 경계선 검출기의 FPGA 설계

  • Ingi Min (Department of Electrical Engineering, Sangmyung University) ;
  • Suhyun Sim (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Seungwon Hwang (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Sunhee Kim (Department of System Semiconductor Engineering, Sangmyung University)
  • 민인기 (상명대학교 전자공학과) ;
  • 심수현 (상명대학교 시스템반도체공학과) ;
  • 황승원 (상명대학교 시스템반도체공학과) ;
  • 김선희 (상명대학교 시스템반도체공학과)
  • Received : 2023.11.10
  • Accepted : 2023.12.12
  • Published : 2023.12.31
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Abstract

Edge detection in image processing and computer vision is one of the most fundamental operations. Canny edge detection algorithm has excellent performance and is currently widely used. However, it is difficult to process the algorithm in real-time because the algorithm is complex. In this study, the equations required in the algorithm were simplified to facilitate hardware implementation, and the calculation speed was increased by using a parallel structure. In particular, the size and management of local buffers were selected in consideration of parallel processing and filter size so that data could be processed without bottlenecks. It was designed in verilog and implemented in FPGA to verify operation and performance.

Keywords

Acknowledgement

다음의 성과는 과학기술정보통신부와 연구개발특구진흥재단이 지원하는 과학벨트 지원사업으로 수행된 연구결과입니다.

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