DOI QR코드

DOI QR Code

Novel DQ transform and time delay module-based phase-locked loop

  • An, Dingguo (School of Electrical Engineering and Automation, Hefei University of Technology) ;
  • Yuan, Lifen (School of Electrical Engineering and Automation, Hefei University of Technology) ;
  • He, Yigang (School of Electrical Engineering, Wuhan University) ;
  • Yin, Baiqiang (School of Electrical Engineering and Automation, Hefei University of Technology) ;
  • Li, Bing (School of Electrical Engineering and Automation, Hefei University of Technology)
  • 투고 : 2021.08.24
  • 심사 : 2022.06.02
  • 발행 : 2022.10.20

초록

The Phase-Locked-Loop (PLL) based on quadrature signal generation (QSG) is widely used in the synchronization units of power systems. Being one of the most popular QSG-PLLs, the time delay unit-based PLL (TD-PLL) is simple and easy to implement. However, when the frequency of the input signal deviates from its rated value, the orthogonality of the QSG output signal and the original input signal cannot be guaranteed, which leads to the generation of double frequency components. To solve this problem, this paper analyzes the generation mechanism for the double frequency component of the TD-PLL. Then, a quadrature signal generation and processing module is built based on a DQ transform and time delay unit to eliminate the double frequency component. This ability is the key part of the proposed PLL (DQ-TD-PLL). Finally, the performance of DQ-TD-PLL is evaluated with simulations and experiments. The obtained results show that the proposed DQ-TD-PLL can eliminate the influence of double frequency component. It can also be seen that the proposed method has better dynamic performance when compared with other methods in the literature.

키워드

과제정보

This work was supported by the State Key Program of National Natural Science Foundation of China under Grant No. 51637004.

참고문헌

  1. Zhou, H., Chen, S., Lai, J., Lu, X., Yu, C., Hu, W., Deng, Q., Zhou, D.: Modeling and synchronization stability of low-voltage active distribution networks with large-scale distributed generations. IEEE Access. 6, 70989-71002 (2018) https://doi.org/10.1109/ACCESS.2018.2881142
  2. Batista, Y.N., de Souza, H.E.P., Neves, F.A.S., Dias Filho, R.F., Bradaschia, F.: Variable-structure generalized delayed signal cancellation PLL to improve convergence time. IEEE Trans. Ind. Electron. 62(11), 7146-7150 (2015) https://doi.org/10.1109/TIE.2015.2443108
  3. Golestan, S., Guerrero, J.M., Abusorrah, A.M., Al-Turki, Y.: Hybrid synchronous/stationary reference-frame-filtering-based PLL. IEEE Trans. Ind. Electron. 62(8), 5018-5022 (2015) https://doi.org/10.1109/TIE.2015.2393835
  4. Lu, Y., Xiao, G., Wang, X., Blaabjerg, F.: Grid synchronization with selective harmonic detection based on generalized delayed signal superposition. IEEE Trans. Power Electron. 33(5), 3938-3949 (2018) https://doi.org/10.1109/TPEL.2017.2721461
  5. Dong, D., Wen, B., Boroyevich, D., Mattavelli, P., Xue, Y.: Analysis of phase-locked loop low-frequency stability in three-phase grid-connected power converters considering impedance interactions. IEEE Trans. Ind. Electron. 62(1), 310-321 (2015) https://doi.org/10.1109/TIE.2014.2334665
  6. Chen, G., Zhang, L., Wang, R., Zhang, L., Cai, X.: A novel SPLL and voltage sag detection based on LES filters and improved instantaneous symmetrical components method. IEEE Trans. Power Electron. 30(3), 1177-1188 (2015) https://doi.org/10.1109/TPEL.2014.2318051
  7. Shitole, A.B., Suryawanshi, H.M., Talapur, G.G., Sathyan, S., Ballal, M.S., Borghate, V.B., Ramteke, M.R., Chaudhari, M.A.: Grid interfaced distributed generation system with modified current control loop using adaptive synchronization technique. IEEE Trans. Ind. Informat. 13(5), 2634-2644 (2017) https://doi.org/10.1109/TII.2017.2665477
  8. Blaabjerg, F., Teodorescu, R., Liserre, M., Timbus, A.V.: Overview of control and grid synchronization for distributed power generation systems. IEEE Trans. Ind. Electron. 53(5), 1398-1409 (2006)
  9. Hadjidemetriou, L., Kyriakides, E., Blaabjerg, F.: A robust synchronization to enhance the power quality of renewable energy systems. IEEETrans. Ind. Electron. 62(8), 4858-4868 (2015) https://doi.org/10.1109/TIE.2015.2397871
  10. Karimi-Ghartemani, M.: A unifying approach to single-phase synchronous reference frame PLLs. IEEE Trans. Power Electron. 28(10), 4550-4556 (2013) https://doi.org/10.1109/TPEL.2012.2235185
  11. Golestan, S., Guerrero, J.M., Vasquez, J.C.: Single-phase PLLs: a review of recent advances. IEEE Trans. Power Electron. 32(12), 9013-9030 (2017) https://doi.org/10.1109/TPEL.2017.2653861
  12. Xu, J., Qian, H., Bian, S., Hu, Y., Xie, S.: Comparative study of single-phase phase-locked loops for grid-connected inverters under non-ideal grid conditions. CSEE J. Power. Energy. Syst. 1-10, (2020)
  13. Qian, H., Xu, J., Xie, S.: Power-based phase-locked loops for single-phase applications-a survey. In 2020 15th IEEE conference on indus-trial electronics and applications (ICIEA). 699-703 (2020)
  14. Yang, Y., Zhou, K., Blaabjerg, F.: Virtual unit delay for digital frequency adaptive T/4 delay phase-locked loop system. In 2016 IEEE 8th international power electronics and motion control conference (IPEMC-ECCE Asia). 2910-2916 (2016)
  15. Lamo, P., Lopez, F., Pigazo, A., Azcondo, F.J.: An efficient fpga implementation of a quadrature signal-generation subsystem in SRF PLLs in single-phase PFCs. IEEE Trans. Power Electron. 32(5), 3959-3969 (2017) https://doi.org/10.1109/TPEL.2016.2582534
  16. Guan, Q., Zhang, Y., Kang, Y., Guerrero, J.M.: Single-phase phase-locked loop based on derivative elements. IEEE Trans. Power Electron. 32(6), 4411-4420 (2017) https://doi.org/10.1109/TPEL.2016.2602229
  17. Xiao, F., Dong, L., Li, L., Liao, X.: A frequency-fixed SOGIbased PLL for single-phase grid-connected converters. IEEE Trans. Power Electron. 32(3), 1713-1719 (2017) https://doi.org/10.1109/TPEL.2016.2606623
  18. Akhtar, M.A., Saha, S.: An adaptive frequency-fixed secondorder generalized integrator-quadrature signal generator using fractional-order conformal mapping based approach. IEEE Trans. Power Electron. 35(6), 5548-5552 (2020) https://doi.org/10.1109/TPEL.2019.2951427
  19. Ikken, N., Bouknadel, A., Haddou, A., Tariba, N.-E., El omari, H., El Omari, H.: PLL synchronization method based on second-order generalized integrator for single phase grid connected inverters systems during grid abnormalities. In 2019 international conference on wireless tech-nologies, embedded and intelligent systems (WITS). 1-5 (2019)
  20. Golestan, S., Guerrero, J.M., Vasquez, J.C.: A nonadaptive window- based PLL for single-phase applications. IEEE Trans. Power Electron. 33(1), 24-31 (2018) https://doi.org/10.1109/TPEL.2017.2713379
  21. Golestan, S., Guerrero, J.M., Vidal, A., Yepes, A.G., Doval-Gandoy, J., Freijedo, F.D.: Small-signal modeling, stability analysis and design optimization of single-phase delay-based PLLs. IEEE Trans. Power Electron. 31(5), 3517-3527 (2016) https://doi.org/10.1109/TPEL.2015.2462082
  22. Golestan, S., Guerrero, J.M., Vasquez, J.C., Abusorrah, A.M., Al-Turki, Y.: Research on variable-length transfer delay, delayedsignal- cancellation-based PLLs. IEEE Trans. Power Electron. 33(10), 8388-8398 (2018) https://doi.org/10.1109/TPEL.2017.2785281
  23. Soni, K.A., Jaiswal, N.K., Lokhandwala, M.A.: Phase locked loop for single phase grid synchronization. In 2018 2nd international conferenceon trends in electronics and informatics (ICOEI). 1058-1063 (2018)
  24. Golestan, S., Guerrero, J.M., Abusorrah, A., Al-Hindawi, M.M., Al-Turki, Y.: An adaptive quadrature signal generation-based single-phase phase-locked loop for grid-connected applications. IEEE Trans. Ind. Electron. 64(4), 2848-2854 (2017) https://doi.org/10.1109/TIE.2016.2555280
  25. Yang, YY., Hadjidemetriou, L., Blaabjerg, F., Kyriakides, E.: Benchmarking of phase locked loop based synchronization techniques for grid-connected inverter systems. 2015 9th international conference on power electronics and ECCE Asia (ICPE-ECCE Asia). 2167-2174 (2015)
  26. Prakash, S., Singh, J.K., Behera, R.K., Mondal, A.: A type-3 modified SOGI-PLL with grid disturbance rejection capability for single-phase grid-tied converters. IEEE Trans. Ind. Appl. 57(4), 4242-4252 (2021) https://doi.org/10.1109/TIA.2021.3079122