반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
권호 표지

동작 분석을 통한 비휘발성 메모리에 대한 Wear-out 공격 방지 기법

Exploiting Memory Sequence Analysis to Defense Wear-out Attack for Non-Volatile Memory

  • 최주희 (상명대학교 스마트정보통신공학과)
  • Choi, Juhee (Dept. of Smart Information Communication Engineering, Sangmyung University)
  • 투고 : 2022.11.24
  • 심사 : 2022.12.13
  • 발행 : 2022.12.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Cache bypassing is a scheme to prevent unnecessary cache blocks from occupying the capacity of the cache for avoiding cache contamination. This method is introduced to alleviate the problems of non-volatile memories (NVMs)-based memory system. However, the prior works have been studied without considering wear-out attack. Malicious writing to a small area in NVMs leads to the failure of the system due to the limited write endurance of NVMs. This paper proposes a novel scheme to prolong the lifetime with higher resistance for the wear-out attack. First, the memory reference pattern is found by modified reuse distance calculation for each cache block. If a cache block is determined as the target of the attack, it is forwarded to higher level cache or main memory without updating the NVM-based cache. The experimental results show that the write endurance is improved by 14% on average and 36% on maximum.

키워드

참고문헌

  1. Jang, Minwoo, et al., "Defending against flush+ reload attack with DRAM cache by bypassing shared SRAM cache." IEEE Access, Vol. 8, pp. 179837-179844, 2020. https://doi.org/10.1109/access.2020.3027946
  2. Egawa, Ryusuke, et al., "A layer-adaptable cache hierarchy by a multiple-layer bypass mechanism." Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies. 2019.
  3. Emara, Moustafa, and Bo-Cheng Lai, "Selective bypassing and mapping for heterogeneous applications on GPGPUs," Journal of Parallel and Distributed Computing, Vol. 142, pp. 106-118, 2020. https://doi.org/10.1016/j.jpdc.2020.04.003
  4. Xu, Yuanchao, et al., "Asymmetry & Locality-Aware Cache Bypass and Flush for NVM-Based Unified Persistent Memory," 2019 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), pp. 168-175, 2019.
  5. Choi, Juhee, "Low Power Scheme Using Bypassing Technique for Hybrid Cache Architecture," Journal of the Semiconductor & Display Technology, Vol. 20, No. 4, pp. 10-15, 2021.
  6. Wang, Guan, et al., "Shared Last-Level Cache Management and Memory Scheduling for GPGPUs with Hybrid Main Memory," ACM Transactions on Embedded Computing Systems (TECS), Vol. 17, No. 4, pp. 1-25, 2018.
  7. Tae Hyun Kim, Yang On, and Sang Yeon Jun, "Design of Asynchronous Non-Volatile Memory Module Using NAND Flash Memory and PSRAM," Journal of the Semiconductor & Display Technology Vol. 19, No.3, pp. 118-123, 2020.
  8. H.-S. Philip Wong et al., "Phase Change Memory," in Proceedings of the IEEE, Vol. 98, No. 12, pp. 2201- 2227, Dec. 2010. https://doi.org/10.1109/JPROC.2010.2070050
  9. Agarwal, Sukarn, and Hemangee K. Kapoor, "Improving the lifetime of non-volatile cache by write restriction," IEEE Transactions on Computers Vol. 68, No. 9. pp. 1297-1312, 2019. https://doi.org/10.1109/tc.2019.2892424
  10. Esfeden, Hodjat Asghari, et al., "BOW: Breathing operand windows to exploit bypassing in GPUs," 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 996-1007, 2020.
  11. Seong, Nak Hee, Dong Hyuk Woo, and Hsien-Hsin S. Lee, "Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping," ACM SIGARCH computer architecture news, Vol. 38, No. 3, pp. 383-394, 2010. https://doi.org/10.1145/1816038.1816014
  12. Cronin, Patrick, Chengmo Yang, and Yongpan Liu, "A collaborative defense against wear out attacks in nonvolatile processors," ACM/ESDA/IEEE Design Automation Conference (DAC), p. 1-6, 2018.
  13. Zhou, Fang, et al., "VAIL: A Victim-Aware Cache Policy to improve NVM Lifetime for hybrid memory system," Parallel Computing, Vol. 87, pp. 70-76, 2019. https://doi.org/10.1016/j.parco.2018.12.005
  14. J. Power, J. Hestness, M. S. Orr, M. D. Hill, and D. A. Wood, "gem5-gpu: A heterogeneous cpu-gpu simulator," IEEE Computer Architecture Letters, Vol. 14, No. 1, pp. 34-36, 2015. https://doi.org/10.1109/LCA.2014.2299539
  15. J. Henning, "Spec cpu2006 benchmark descriptions," SIGARCH Comput. Archit. News, Vol. 34, No. 4, pp. 1-17, 2006. https://doi.org/10.1145/1186736.1186737
  16. Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, and Yuan Xie, "Energy- and endurance-aware design of phase change memory caches," 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp. 136-141, 2010.