반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
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CIC 필터를 이용한 저면적 데시메이션 필터 설계

Design of Low Area Decimation Filters Using CIC Filters

  • 김선희 (상명대학교 시스템반도체공학과) ;
  • 오재일 (상명대학교 전자정보시스템공학과) ;
  • 홍대기 (상명대학교 시스템반도체공학과)
  • Kim, Sunhee (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Oh, Jaeil (Department of Electronic Information System Engineering, Sangmyung University) ;
  • Hong, Dae-ki (Department of System Semiconductor Engineering, Sangmyung University)
  • 투고 : 2021.08.27
  • 심사 : 2021.09.11
  • 발행 : 2021.09.30
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초록

Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.

키워드

과제정보

이 논문은 2021년 해양수산부 재원으로 해양수산과학기술진흥원의 지원을 받아 수행된 연구임(분산형 수중관측 제어망 개발).

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