Journal of Power Electronics

  • 제21권11호
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  • Pages.1690-1700
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  • 2021
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  • 1598-2092(pISSN)
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  • 2093-4718(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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Design rule for fault-tolerant converters of switched reluctance motors

  • Fang, Chenghui (School of Electrical and Power Engineering, China University of Mining and Technology) ;
  • Chen, Hao (School of Electrical and Power Engineering, China University of Mining and Technology)
  • 투고 : 2021.05.12
  • 심사 : 2021.08.26
  • 발행 : 2021.11.20
⟨ 이전 논문 다음 논문 ⟩

초록

To enhance the reliability of converters, many fault-tolerant converters have been proposed in the literature. However, the design rule is seldom proposed. The converter is usually a switch circuit that can be described by the matrix; therefore, the design of a fault-tolerant converter can be transformed to the matrix design. The fault tolerance of a circuit is mainly determined by its alternative loops. In this study, minus-1 Boolean determinant is defined to establish a relationship between the matrix and the alternative loop. Then, the following proposition is proven: for a connection matrix of a circuit, the minus-1 Boolean determinant represents the sum of loops in the circuit, where each term of the minus-1 Boolean determinant represents a loop of the circuit. The asymmetric half bridge converter is the most commonly used converter of the switched reluctance motor (SRM). According to its connection matrix, its candidate fault-tolerant converters are listed, and with the proposition, their alternative loops are obtained, their fault tolerance performance is evaluated, and the optimal one is selected. Furthermore, the fault tolerance performance of the derived converter is tested by simulations and experiments on a 12/8 SRM.

키워드

과제정보

This work is supported by the National Natural Science Foundation of China-NSFC-ASRT (Chinese-Egyptian) Cooperative Research Project under Grant No. 51961145401.

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