DOI QR코드

DOI QR Code

Low-loss carrier-stored IGBT with p-type Schottky diode-clamped shielding layer

  • Yi, Bo (School of Electronic Science and Engineering, University of Electronic Science and Technology of China) ;
  • Zhao, Qing (School of Electronic Science and Engineering, University of Electronic Science and Technology of China) ;
  • Zhang, Qian (School of Materials and Energy, University of Electronic Science and Technology of China) ;
  • Cheng, JunJi (School of Electronic Science and Engineering, University of Electronic Science and Technology of China) ;
  • Huang, HaiMeng (School of Electronic Science and Engineering, University of Electronic Science and Technology of China) ;
  • Pan, YiLan (School of Materials and Energy, University of Electronic Science and Technology of China) ;
  • Hu, XiaoRan (School of Materials and Energy, University of Electronic Science and Technology of China) ;
  • Xiang, Yong (School of Materials and Energy, University of Electronic Science and Technology of China)
  • Received : 2020.12.17
  • Accepted : 2021.05.04
  • Published : 2021.08.20

Abstract

A novel carrier-stored trench bipolar transistor (CSTBT) with heavily doped carrier-stored layer (CSL) is proposed and investigated by TCAD tools. The voltage of CSL is shielded by a buried p-type layer (P-bury) whose potential is clamped by a p-type Schottky Barrier Diode (pSBD) in series-connection with a PN diode. Hence, the CSL can be heavily doped, and the trade-off between on-state voltage drop (Von) and turn-off loss (Eoff) is substantially improved. Compared with that of a conventional CSTBT with floating P-base (FP-CSTBT), the Eoff of the proposed CSTBT is reduced by 27.9% at Von=1.1 V. Owing to the shielding effect of the P-bury layer, the saturation current density of the proposed CSTBT is reduced by 52% compared with that of the FP-CSTBT. Consequently, significantly enlarged short-circuit safe operation area is obtained, and the short-circuit withstand time (tsc) is increased to 12.8 s at ultra-low Von (~1.1 V).

Keywords

Acknowledgement

This work was supported in part by the National Natural Science Foundation of China under Grant 61804021, in part by the Fundamental Research Funds for the Central Universities under Grant ZYGX2019J020, and in part by the scholarship from China Scholarship Council under the Grant 201908515126.

References

  1. Wang, H., Su, M., Sheng, K.: Theoretical performance limit of the IGBT. IEEE Trans. Electron Devices 64(1), 4184-4192 (2017) https://doi.org/10.1109/TED.2017.2737021
  2. Takahashi H, Tomomatsu Y, Sato I: CSTBT (III) as the next generation IGBT. In: Proceeding 2008 IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp 72-75, (2008).
  3. Hu J, Bobde M, Yilmaz H, Bhalla A: Trench shielded planar gate IGBT (TSPG-IGBT) for low loss and Robust Short-Circuit Capalibity. In: Proceeding 2013 IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD), 25-28, 2013.
  4. Reigosa PD, Iannuzzo F, Rahimo M, Corvasce C, Blaabjerg F: Increasing emitter efficiency in 3.3 kV enhanced trench IGBTs for higher short-circuit capability". In: Proceeding 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), pp 1722-1728, (2018).
  5. Rahman MT, Kimura K, Fukami T, Konishi M, Nishiwaki T, Saito J, Hamada, K: A novel carrier accumulating structure for 1200V IGBTs without negative capacitance and decreasing breakdown-voltage. In: Proceeding 2008 IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp 491-494, (2018).
  6. Antoniou, M., Lophitis, N., Bauer, F., Nistor, I., Bellini, M., Rahimo, M., Udrea, F.: Novel approach toward plasma enhancement in trench-insulated gate bipolar transistors. IEEE Electron Device Lett. 36(8), 823-825 (2015) https://doi.org/10.1109/LED.2015.2433894
  7. Mori, M., Oyama, K., Arai, T., Sakano, J., Nishimura, Y., Masuda, K., Homma, H.: A planar-gate high-conductivity IGBT (HiGT) with hole-barrier layer. IEEE Trans. Electron Devices 54(6), 1515-1520 (2007) https://doi.org/10.1109/TED.2007.895874
  8. Li P, Kong MF, Chen XB: A novel diode-clamped CSTBT with ultra-low on-state voltage and saturation current. In: Proceeding 2016 IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp 307-310, (2016).
  9. Sumitomo M, Asai J, Sakane H, Arakawa K, Higuchi Y, Matsui M: Low loss IGBT with partially narrow mesa structure (PNM-IGBT). In: Proceeding 2012 IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp 17-20, (2012).
  10. Huang, M.M., Gao, B., Yang, Z., Lai, L., Gong, M.: A Carrier-Storage-Enhanced Superjunction IGBT With Ultralow Loss and On-State Voltage. IEEE Electron Device Lett. 39(2), 264-267 (2018) https://doi.org/10.1109/led.2017.2788458
  11. Antoniou M, Udrea F, Bauer F: Optimisation of superjunction bipolar transistor for ultra-fast switching applications. In: Proceeding 2007 IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD), (2007).
  12. Yi, B., Xie, X.T., Kong, M.F., Cheng, J.J., Chen, X.B.: A novel diode-clamped carrier stored trench IGBT with improved performances. IEEE Trans. Electron Devices 67(1), 243-248 (2020) https://doi.org/10.1109/ted.2019.2955820
  13. Li, P., Lyu, X.L., Cheng, J.J., Chen, X.B.: A low on-state voltage and saturation current TIGBT with self-biased pMOS. IEEE Electron Device Lett. 37(11), 1470-1472 (2016) https://doi.org/10.1109/LED.2016.2614514
  14. Pyo, J., Ryu, H.Y., Park, J., Lee, M., Ryu, H.Y.: Laser-power dependence of poly-silicon crystallization using 355 nm nanosecond laser annealing. J. Korean Phys. Soc. 76(12), 1116-1120 (2020) https://doi.org/10.3938/jkps.76.1116
  15. Gejo R, Ogura T, Misu S, Nakamura K, Yasuhara N, Takano A: Ideal carrier profile control for high-speed switching of 1200 V IGBTs. In: Proceeding 2014 IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp 99-102, (2014).
  16. Sze, S.M., K Ng, K.: Physics of semiconductor devices. John Wiley & Sons (2006)
  17. Smith, B.L., Rhoderick, E.H.: Schottky barriers on p-type silicon. Solid-State Electron. 14(1), 71-75 (1971) https://doi.org/10.1016/0038-1101(71)90049-9
  18. Korchnoy V: Investigation of Choline Hydroxide for Selective Silicon Etch from a Gate Oxide Failure Analysis Standpoint. In: International Symposium for testing and failure analysis, pp 325-332, (2002).
  19. Hsieh APS, Camuso G, Udrea F, Ng C, Tang Y, Vytla RK, Charles A: Superjunction IGBT vs. FS IGBT for 200℃ operation. In: Proceeding 2016 IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp 137-140. (2015).
  20. Donlon JF, Motto ER, Takahashi T, Fujii H, Satoh K: Chip improvements for future IGBT modules. IEEE Industry Applications Society Annual Meeting, pp 1-7, (2008).
  21. Nakagawa A: Theoretical investigation of silicon limit characteristics of IGBT. In: Proceeding 2006 IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD), (2006).
  22. Jorda, X., Perpina, X., Vellvehi, M., Coleto, J.: Power-substrate static thermal characterization based on a test chip. IEEE Trans. Device Mater. Reliab. 8(4), 671-679 (2008) https://doi.org/10.1109/TDMR.2008.2005299
  23. Jiang, M.X., Shen, Z.J.: Simulation study of an injection enhanced insulated-gate bipolar transistor with p-base schottky contact. IEEE Trans. Electron Device 63(5), 1991-1995 (2016) https://doi.org/10.1109/TED.2016.2543244