과제정보
This paper was supported by the Research Fund, 2019, Pyeongtaek University in Korea
참고문헌
- B. Yoon and S. Yoo, "Maples navigation based on DQN considering moving obstacles, and traing time reduction algorithm," Journal of the Korea Instiute of Information and Comunication Enginering, vol. 25, no. 3, pp. 377-383, Mar. 2021.
- M. Perenzoni, D. Perenzoni, and D. Stoppa, "A 64×64-pixels digital silicon photomultiplier direct TOF sensor with 100-MPhotons/s/pixel background rejection and imaging/altimeter mode with 0.14% precision up to 6 km for spacecraft navigation and landing," IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 151-160, Jan. 2017. https://doi.org/10.1109/JSSC.2016.2623635
- F. M. D. Rocca, H. Mai, S. W. Hutchings, T. A. Abbas, K. Buckbee, A. Tsiamis, P. Lomax, I. Gyongy, N. A. W. Dutton, and R. K. Henderson, "A 128x128 SPAD motion-triggered time-of-flight image sensor with in-pixel histogram and column-parallel vision processor," IEEE J. Solid-State Circuits, vol. 55, no. 7, pp. 1762-1775, Jul. 2020. https://doi.org/10.1109/JSSC.2020.2993722
- M. L. Hafiane, W. Wagner, Z. Dibi, and O. Manck, "Depth resolution enhancement technique for CMOS time-of-flight 3-D image sensors," IEEE Sensors J., vol. 12, no. 6, pp. 2320-2327, Jun. 2012. https://doi.org/10.1109/JSEN.2012.2187350
- M. Liu, H. Liu, X. Li, and Z. Zhu "A 60-m range 6.16-mW laser-power linear-mode LiDAR system with multiplex ADC/TDC in 65-nm CMOS," IEEE Trans. Circuits Syst. I Reg. Papers, vol. 67, no. 3, pp. 753-764, Mar. 2020. https://doi.org/10.1109/TCSI.2019.2955671
- C. Hong, S. Kim, J. Kim, and S. M. Park, "A linear-mode LiDAR sensor using a multi-channel CMOS transimpedance amplifier array," IEEE Sensors J., vol. 18, no. 17, pp. 7032-7040, Sep. 2018. https://doi.org/10.1109/JSEN.2018.2852794
- Y. Wang, X. Zhou, Z. Song, J. Kuang, and Q. Cao, "A 3.0-ps rms precision 277-MSamples/s throughput time-to-digital converter using multi-edge encoding scheme in a Kintex-7 FPGA," IEEE Trans. Nucl. Sci., vol. 66, no. 10, pp. 2275-2281, Oct. 2019. https://doi.org/10.1109/tns.2019.2938571
- P. Kwiatkowski and R. Szplet, "Efficient Implementation of Multiple Time Coding Lines-Based TDC in an FPGA Device," IEEE Trans. Instrum. Meas., vol. 69, no. 10, pp. 7353-7364, 2020. https://doi.org/10.1109/tim.2020.2984929
- H. Wang, F. F. Dai, and H. Wang, "A reconfigurable Vernier time-to-digital converter with 2-D spiral comparator array and second-order ΔΣ linearizatio," IEEE J. Solid-State Circuits, vol. 53, no. 3, pp. 738-749, Mar. 2018. https://doi.org/10.1109/JSSC.2017.2788872
- L. Perktold and J. Christiansen, "A fine time-resolution (3 ps-rms) time-to-digital converter for highly integrated designs," in Proc. IEEE Int. Instrum. Meas. Technol. Conf. (I MTC), Minneapolis: MN, pp. 1092-1097, May. 2013.
- B. Markovic, S. Tisa, F. A. Villa, A. Tosi, and F. Zappa, "A high linearity, 17 ps precision time-to-digital converter based on a single-stage Vernier delay loop fine interpolation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 3, pp. 557-569, Mar. 2013. https://doi.org/10.1109/TCSI.2012.2215737
- J. P. Jansson, P. Keranen, S. Jahromi, and J. Kostamovaara, "Enhancing nutt-based time-to-digital converter performance with internal systematic averaging," IEEE Trans. Instrum. Meas., vol. 69, no. 6, pp. 3928-3935, Jun. 2020. https://doi.org/10.1109/tim.2019.2932156