Journal of Power Electronics

  • 제20권5호
  • /
  • Pages.1328-1341
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  • 2020
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  • 1598-2092(pISSN)
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  • 2093-4718(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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An efficient hybrid digital architecture for space vector PWM method for multilevel VSI

  • Anjana, K.G. (Department of Electrical and Electronics Engineering, National Institute of Technology) ;
  • Aswini Kumar, M. (Department of Electrical and Electronics Engineering, National Institute of Technology) ;
  • Biswas, Jayanta (Department of Computer Science, Christ University) ;
  • Barai, Mukti (Department of Electrical and Electronics Engineering, National Institute of Technology)
  • 투고 : 2020.02.17
  • 심사 : 2020.06.30
  • 발행 : 2020.09.20
⟨ 이전 논문 다음 논문 ⟩

초록

This paper presents an efficient, cost effective design implementation of a hybrid digital architecture for space vector pulse width modulation (SVPWM) method for multilevel inverters (MLIs). The SVPWM method is one of the most popular real time PWM method for three phase voltage source inverter (VSI). The implementation of SVPWM method becomes complex with an increase in the number of levels in a multilevel inverter. The SVPWM method for multilevel inverter is a multitask system. The main constraint when it comes to implementing SVPWM for multilevel inverters is the processing of dwell time computation and the generation of PWM gate signals for all of the switches with an accurate delay. A hybrid hardware structure consisting of a simple low-cost, low-power dsPIC micro controller (dsPIC 30F4011) and a state of the art Field Programmable Gate Array (FPGA) (Cyclone V 5CGXFC5C6F27C7N) is used to implement SVPWM. The proposed hybrid digital architecture utilizes the advantages and resources of the dsPIC and FPGA. The hybrid digital architecture meets the timing constraints of multitasking through synchronization and parallelism. A communication interface between the dsPIC and the FPGA reduces the design complexity. The software overhead for the communication interface remains fixed for any number of levels. The hybrid structure of the digital architecture provides scalability for the SVPWM method with more number of levels in multilevel inverter. The operation of the proposed hybrid digital architecture is experimentally validated with an optimized SVPWM method for a five level VSI. An optimized region identification algorithm and simple dwell time expressions are described for a five level SVPWM. The input DC of the five level VSI is obtained from a differential power processing (DPP) based PV system. Experimental results under different operating conditions are presented.

키워드

참고문헌

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