반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
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반도체 전공정의 하드마스크 스트립 검사시스템 개발

Development of Hard Mask Strip Inspection System for Semiconductor Wafer Manufacturing Process

  • Lee, Jonghwan (School of Industrial Engineering Kumoh National Institute of Technology) ;
  • Jung, Seong Wook (DH Tach) ;
  • Kim, Min Je (School of Industrial Engineering Kumoh National Institute of Technology)
  • 투고 : 2020.08.27
  • 심사 : 2020.09.11
  • 발행 : 2020.09.30
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초록

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

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참고문헌

  1. Yong Huang, Jialei Liu, Zhiyong, Jing Zhao and Huanxin Liu, "Optimization of Wet Strip after Metal Hard Mask All-in-One Etch for metal void reduction and yield improvement," China Semiconductor Technology International Conference, 2017.
  2. Hyunwoo Oh and Woongsik Kim, "The Development of Bumped Wafer Inspection System Using the Confocal Principle," J. of The Institute of Electronics and Information Engineers, Vol. 7, pp. 47-54, 2019.
  3. Y-H Yoo, H-J Cho, J-W Yim, D-C Kim and S-H Shin, "Defect Inspection of Phase Shift Photo-Mask with Digital Hologram Microscope," Korean Journal of Optics and Photonics, Vol. 5, pp. 303-308, 2007.
  4. Y. J. Kim, K. Hibino, Y. Bitou, S. Osawa, N. Sugita, and M. Mitsuishi, "Measurement of Absolute Optical Thickness Distribution of Semiconductor Wafer Using a Wavelength Tuning Interferometer", Korean Society for Precision Engineering, Vol. 6, pp. 249-250, 2009.
  5. G. B. Kim, "Development of Inspection System with Optical Scanning Mechanism and Near-Infrared Camera Optics for Solar Cell Wafer", Journal of the Semiconductor & Display Technology, Vol. 11. No. 3, pp. 1-6, 2012.
  6. E. Y. Lee and M. K. Kim, "Evaluation of the Machining Method on the Formation of Surface Quality of Upper Electrode for Semiconductor Plasma Etch Process", Journal of the Semiconductor & Display Technology, Vol. 18. No. 4, pp. 1-5, 2019.