전기전자학회논문지 (Journal of IKEEE)

  • 제24권3호
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  • Pages.890-894
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  • 2020
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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Parallel PNP 및 N+ drift가 삽입된 높은 홀딩전압특성을 갖는 ESD보호회로에 관한 연구

A Study on ESD Protection Circuit with High Holding Voltage with Parallel PNP and N+ difrt inserted

  • 투고 : 2020.09.15
  • 심사 : 2020.09.28
  • 발행 : 2020.09.30
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초록

본 논문에서는 대표적인 ESD 보호소자인 LVTSCR의 구조적 변화를 통해 높은 홀딩전압 특성을 가지는 ESD 보호소자를 제안한다. 제안된 ESD 보호소자는 병렬 PNP path와 긴 N+ drift 영역을 삽입하여 기존의 LVTSCR보다 높은 홀딩전압을 가지며, 일반적인 SCR 기반 ESD보호소자의 단점인 Latch-up 면역특성을 향상시킨다. 또한 기생 BJT들의 유효 베이스 폭을 설계변수로 설정하였으며, N-Stack 기술을 적용하여 요구되는 application에 적용할 수 있도록 시놉시스사의 TCAD 시뮬레이션을 통해 제안된 ESD 보호소자의 전기적 특성을 검증하였다.

In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.

키워드

참고문헌

  1. Y. C. Huang and M. D. Ker, "A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-um 5-V CMOS Process," IEEE Electron Device Letters, vol.34, no.5, pp.674-676, 2013. DOI: 10.1109/LED.2013.2252456
  2. Z. Wang, R. C. Sun, J. J. Liou and D. G. Liu, "Optimized pMOS-Triggered Bidirectional SCR for Low-Voltage ESD Protection Applications," IEEE Transactions on Electron Devices, vol.61, no.7, pp.2588-2594, 2014. DOI: 10.1109/TED.2014.2320827
  3. F. Ma, B. Zhang, Y. Han, J. Zheng, B. Song, S. Dong and H. Liang, "High Holding Voltage SCR-LDMOS Stacking Structure With Ring- Resistance-Triggered Technique," IEEE Electron Device Letters, vol.34, no.9, pp.1178-1180, 2013. DOI: 10.1109/LED.2013.2272591
  4. M. D. Ker and K. C. Hsu, "Overview of onchip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits," IEEE Transactions on Device and Materials Reliability, vol.5, no.2, pp.235-249, 2005. DOI: 10.1109/TDMR.2005.846824
  5. Z. Liu, J. J. Liou, S. Dong, and Y. Han, "Silicon-Controlled Rectifier Stacking Structure for High-Voltage ESD Protection Applications," IEEE Electron Devices Letters, vol.31, no.8, pp. 845-847, 2010. DOI: 10.1109/LED.2010.2050575

피인용 문헌

  1. 향상된 전기적 특성을 지닌 LVTSCR 기반의 N-Stack ESD 보호소자에 관한 연구 vol.25, pp.1, 2020, https://doi.org/10.7471/ikeee.2021.25.1.168