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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Design and Implementation of Accelerator Architecture for Binary Weight Network on FPGA with Limited Resources

한정된 자원을 갖는 FPGA에서의 이진가중치 신경망 가속처리 구조 설계 및 구현

  • Received : 2020.03.06
  • Accepted : 2020.03.23
  • Published : 2020.03.31
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Abstract

In this paper, we propose a method to accelerate BWN based on FPGA with limited resources for embedded system. Because of the limited number of logic elements available, a single computing unit capable of handling Conv-layer, FC-layer of various sizes must be designed and reused. Also, if the input feature map can not be parallel processed at one time, the output must be calculated by reading the inputs several times. Since the number of available BRAM modules is limited, the number of data bits in the BWN accelerator must be minimized. The image classification processing time of the BWN accelerator is superior when compared with a embedded CPU and is faster than a desktop PC and 50% slower than a GPU system. Since the BWN accelerator uses a slow clock of 50MHz, it can be seen that the BWN accelerator is advantageous in performance versus power.

본 연구에서는 임베디드 시스템에 적용하기 위해 자원이 제한된 조건의 FPGA를 기반으로 BWN 가속처리를 하는 방법을 제시하였다. 사용할 수 있는 로직의 개수가 제한적이기 때문에 다양한 크기의 Conv-layer, FC-layer를 처리할 수 있는 하나의 연산장치를 설계해서 재활용하였다. Input feature map 데이터를 한번에 병렬처리를 할 수 없는 경우 데이터를 여러 번 읽어서 중간결과를계산하고 합산하여 최종 출력을 계산하였다. 사용할 수 있는 BRAM 모듈 개수가 제한적이기 때문에 BWN 가속기내의 데이터 bit수를 최소화한 구조를 사용하였다. 구현한 BWN가속기의 이미지 분류 처리 시간은 소형 시스템과 비교하였을 때 처리시간 측면에서 우수함을 보였고 고성능 시스템과 비교하였을 때는 데스크탑 PC보다는 빠르고 높은 클럭속도의 GPU시스템의 50%정도 느렸다. BWN가속기는 50MHz의 느린 clock을 사용하므로 성능대비 전력측면에서 유리함을 확인할 수 있었다.

Keywords

References

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