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An Aging Measurement Scheme for Flash Memory Using LDPC Decoding Information

  • Kang, Taegeun (Dept. of Computer Engineering, Hanbat National University) ;
  • Yi, Hyunbean (Dept. of Computer Engineering, Hanbat National University)
  • 투고 : 2019.11.11
  • 심사 : 2020.01.14
  • 발행 : 2020.01.31

초록

웨어-레벨링과 오류정정코드는 플래시 메모리의 신뢰성과 내구성을 위한 필수적인 기술이다. 플래시 메모리를 구성하는 요소들은 사용횟수에 따른 노화도가 서로 다를 수 있다. 따라서 기존의 쓰기/지우기 횟수를 바탕으로 하는 웨어-레벨링 기술은 요소들의 실제 노화도 차이를 반영하기에 충분하지 않다. 본 논문에서는 높은 오류정정율이 증명된 Low-Dencity Parity-Check (LDPC) 코드를 적용하고 복호 과정에서 나오는 정보를 이용하여 플래시 메모리의 실제 노화도를 측정하는 방법을 소개한다. 실험에서는 실제 플래시 메모리를 대상으로 측정한 오류율 데이터를 기반으로 LDPC 코드 복호 정보가 플래시 메모리 각 블록의 노화도를 나타낼 수 있음을 보인다. 또한, 웨어-레벨링 시뮬레이션을 통하여 제안하는 노화도 측정 방법 기반의 웨어-레벨링의 효과를 입증한다.

Wear-leveling techniques and Error Correction Codes (ECCs) are essential for the improvement of the reliability and durability of flash memories. Low-Density Parity-Check (LDPC) codes have higher error correction capabilities than conventional ECCs and have been applied to various flash memory-based storage devices. Conventional wear-leveling schemes using only the number of Program/Erase (P/E) cycles are not enough to reflect the actual aging differences of flash memory components. This paper introduces an actual aging measurement scheme for flash memory wear-leveling using LDPC decoding information. Our analysis, using error-rates obtained from an flash memory module, shows that LDPC decoding information can represent the aging degree of each block. We also show the effectiveness of the wear-leveling based on the proposed scheme through wear-leveling simulation experiments.

키워드

참고문헌

  1. R. Micheloni, A. Marelli, and R. Ravasio, "Error Correction Codes for Non-Volatile Memories," Springer, 2008.
  2. J. C. Moreira and P. G. Farrell, "Essentials of Error-Control Coding," John Wiley and Sons, 2006.
  3. R. G. Gallager, "Low Density Parity Check Codes," IRE Transactions on Information Theory, vol. 8, no. 1, pp. 21-28, Jan. 1962. https://doi.org/10.1109/TIT.1962.1057683
  4. G. Dong, N. Xie, and T. Zhang, "On the Use of Soft-Decision Error-Correction Codes in NAND Flash Memory," IEEE Transactions on Circuits and Systems I, vol. 58, no. 2, pp. 429-439, Feb. 2011. https://doi.org/10.1109/TCSI.2010.2071990
  5. J. Kim and W. Sung, "Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1004-1015, May 2014. https://doi.org/10.1109/TVLSI.2013.2265314
  6. Y. Cai, et al, "Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives," Proceedings of the IEEE, vol. 105, no. 9, pp. 1666-1704, Sep. 2017. https://doi.org/10.1109/JPROC.2017.2713127
  7. R. Bez, et al, "Introduction to Flash Memory," Proceedings of the IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003. https://doi.org/10.1109/JPROC.2003.811702
  8. N. Mielke, et al, "Bit Error Rate in NAND Flash Memories," 2008 IEEE International Reliability Physics Symposium, pp. 9-19, May. 2008.
  9. L.-P. Chang, "On Efficient Wear Leveling for Large-Scale Flash-Memory Storage Systems," Proceedings of the 2007 ACM symposium on Applied computing, pp 1126-1130, Mar. 2007.
  10. Y.-H. Chang, J.-W. Hsieh, and T.-W. Kuo, "Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design," 2007 44th ACM/IEEE Design Automation Conference, pp. 212-217, Jun. 2007.
  11. M. Murugan and D.H.C. Du, "Rejuvenator: A Static Wear Leveling Algorithm for NAND Flash Memory with Minimized Overhead," 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST), May 2011.
  12. Y. Pan, G. Dong, and T. Zhang, "Error Rate-Based Wear-Leveling for Nand Flash Memory at Highly Scaled Technology Nodes," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 7, pp. 1350-1354, Jul. 2013. https://doi.org/10.1109/TVLSI.2012.2210256
  13. B. Peleato, et al, "BER-Based Wear Leveling and Bad Block Management for NAND Flash," 2015 IEEE International Conference on Communications (ICC), pp. 295-300, Jun. 2015.
  14. X. Shi, et al, "Program Error Rate-based Wear Leveling for NAND Flash Memory," 2018 Design, Automation and Test in Europe Conference & Exhibition (DATE), pp. 1241-1246, Mar. 2018.
  15. M. Karimi and A. H. Banihashemi, "On Characterization of Elementary Trapping Sets of Variable-Regular LDPC codes," IEEE Transactions on Information Theory, vol. 60, no. 9, pp. 5188-5203, Sep. 2014. https://doi.org/10.1109/tit.2014.2334657
  16. S. Laendner and O. Milenkovic, "LDPC Codes Based on Latin Squares: Cycle Structure, Stopping Set, and Trapping Set Analysis," IEEE Transactions on Communications, vol. 55, no. 2, pp. 303-312, Feb. 2007. https://doi.org/10.1109/TCOMM.2006.888633
  17. M. P. C. Fossorier, "Quasi-Cyclic Low-Density Parity-Check Codes from Circulant Permutation Matrices," IEEE Transactions on Information Theory, vol. 50, no. 8, pp. 1788-1793, Aug. 2004. https://doi.org/10.1109/TIT.2004.831841
  18. C. Yoon, et al, "Arbitrary Bit Generation and Correction Technique for Encoding QC-LDPC Codes with Dual-Daigonal Parity Structure," 2007 IEEE Wireless Communications and Networking Conference, pp. 663-667, Mar. 2007.
  19. J. Chen, et al, "Reduced-Complexity Decoding of LDPC Codes," IEEE Transactions on Communications, vol. 53, no. 8, pp. 1288-1299, Aug. 2005. https://doi.org/10.1109/TCOMM.2005.852852