Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Recent Trends on High-Speed Duobinary Transceiver Architecture

고속 듀오바이너리 송수신단 설계기술 동향

  • Nam, Han-min (Department of Semiconductor and Display Engineering, Sungkyunkwan University) ;
  • Kong, Bai-Sun (Department of Semiconductor and Display Engineering, Sungkyunkwan University)
  • Received : 2019.09.05
  • Accepted : 2019.09.27
  • Published : 2019.09.30
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Abstract

This paper describes high-speed duobinary transceiver design techniques which are widely used to increase data-rate despite limited channel bandwidth. At high data-rate, signal level is severely degraded as signal frequency becomes larger than the channel bandwidth. Mathematically, a duobinary signal has lower frequency components compared to a Non-Return-to-Zero signal for the same data-rate. Therefore, by using the duobinary signaling, the signal loss can be effectively reduced in physical channel environment as compared to the Non-Return-to-Zero signaling. The mathematical basis of duobinary signaling, and its applications to high-speed transceiver design are investigated in this paper.

본 논문에서는 데이터 전송 속도를 제한하는 채널의 대역폭 문제를 해결하기 위한 방법으로 널리 사용되는 고속 듀오바이너리(duobinary) 송수신단 설계기술 동향을 서술한다. 고속 전송 환경에서는 전송 신호의 주파수가 채널의 대역폭보다 커지게 되어 신호의 손실이 극심해지는 문제가 생긴다. 듀오바이너리 신호는 같은 전송속도를 가지는 Non-Return-to-Zero 신호와 비교했을 때 수식적으로 더 낮은 주파수 대역폭을 가진다. 따라서 고주파 신호일수록 손실정도가 커지는 실제 데이터 채널 환경에서 듀오바이너리 신호기법을 사용함으로써 신호 손실을 효과적으로 줄일 수 있다. 이러한 듀오바이너리 신호기법의 수학적 분석과 더불어 듀오바이너리 신호기법을 고속 송수신단 설계에 적용한 여러 방법들에 대해 탐구한다.

Keywords

References

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