정보처리학회논문지:컴퓨터 및 통신 시스템 (KIPS Transactions on Computer and Communication Systems)

  • 제8권7호
  • /
  • Pages.159-166
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  • 2019
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  • 2287-5891(pISSN)
  • /
  • 2734-049X(eISSN)
한국정보처리학회 (Korea Information Processing Society)
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HMB를 지원하는 DRAM-Less NVMe SSD의 성능 평가

Performance Evaluation of HMB-Supported DRAM-Less NVMe SSDs

  • 김규식 (광운대학교 컴퓨터공학과) ;
  • 김태석 (광운대학교 컴퓨터정보공학부)
  • 투고 : 2019.01.17
  • 심사 : 2019.03.27
  • 발행 : 2019.07.31
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⟨ 이전 논문 다음 논문 ⟩

초록

상용화된 많은 SSD와 달리 DRAM-less SSD는 원가절감, 전력소모량 감소 등의 이유로 DRAM을 가지고 있지 않다. 따라서 DRAM의 부재로 인해 입출력 성능이 저하될 가능성이 존재하며, 이는 호스트의 메모리 일부를 SSD 컨트롤러가 사용할 수 있는 NVMe 인터페이스의 HMB 기능을 통해 개선할 여지가 있다. 본 논문에서는 현재 상용화된 여러 DRAM-less SSD가 DRAM을 가지고 있는 동급 SSD에 비해 실제로 입출력 성능이 떨어지지만 HMB 기능을 사용해 일부 개선하고 있으며, 이는 SSD 컨트롤러가 호스트의 메모리를 매핑테이블 캐시로 주로 사용하고 있기 때문이라는 점을 다양한 실험을 통해 증명한다.

Unlike modern Solid-State Drives with DRAM, DRAM-less SSDs do not have DRAM because they are cheap and consume less power. Obviously, they have performance degradation problem due to lack of DRAM in the controller and this problem can be alleviated by utilizing host memory buffer(HMB) feature of NVMe, which allows SSDs to utilize the DRAM of host. In this paper, we show that commercial DRAM-less SSDs surely exhibit lower I/O performance than other SSDs with DRAM, but they can be improved by utilizing the HMB feature. Through various experiments and analysis, we also show that DRAM-less SSDs mainly exploit the DRAM of host as mapping table cache rather than read cache or write buffer to improve I/O performance.

키워드

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Fig. 1. Results of fio by Workloads and I/O Types

JBCRIN_2019_v8n7_159_f0002.png 이미지

Fig. 2. Roles of HMB

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Fig. 3. Existence of Read Cache in HMB

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Fig. 4. Existence of Write Buffer in HMB

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Fig. 5. Existence of Mapping Table Cache in HMB

Table 1. Tested SSDs

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Table 2. Host PC Environment

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Table 3. Workloads of Fio

JBCRIN_2019_v8n7_159_t0003.png 이미지

참고문헌

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