그림 2. NWCM 측정 구성 Fig. 2. Measurement set-up of NWCM.
그림 3. 온-웨이퍼형 DUT의 구성 Fig. 3. Configuration of on-wafer type DUT.
그림 4. 프로브와 선로가 결합된 2-포트 회로망 Fig. 4. Cascaded connection of probe and microstrip line.
그림 5. 프로브와 선로가 결합된 구조의 2-포트 S-파라미터 측정구성 Fig. 5. 2-port S-parameter measurement set-up for combined structure of probe and microstrip line.
그림 6. TRL 교정용 기판 구성 Fig. 6. Configuration of substrate for TRL calibration.
그림 7. 바이어스-티의 삽입손실 측정결과 Fig. 7. Measurement results of insertion loss for bias-tee.
그림 8. 제작된 TRL 교정용 기판 Fig. 8. Fabricated substrate for TRL calibration.
그림 9. 프로브와 선로가 결합된 구조의 2-포트 S-파라미터 검증을 위한 측정 Fig. 9. Measurement for 2-port S-parameter verification of combined structure of probe and microstrip line.
그림 10. Sm1 + Sm2와 St의 측정결과 비교 Fig. 10. Comparison of measurement results for Sm1+Sm2 and St.
그림 11. MGA-72543 칩이 조립된 온-웨이퍼형 DUT Fig. 11. On-wafer type DUT composed of MGA-72543 chip.
그림 12. MGA-72543 칩의 S-파라미터 측정결과 Fig. 12. S-parameter measurement results of MGA-72543 chip.
그림 13. 온-웨이퍼 DUT 측정을 위한 장비 구성 Fig. 13. Instrumentation set-up for on-wafer type DUT measurement.
그림 14. MGA-72543 칩의 잡음 파라미터 측정결과 Fig. 14. Noise parameter measurement results of MGA-72543.
그림 1. S-행렬과 잡음파를 이용한 2-포트 회로망의 표현 Fig. 1. Representation of a two-port network using S-matrix and noise wave.
표 1. 반복 측정에 대한 측정결과들의 최대 표준편차 Table 1. The maximum standard deviation of the measurement results for repeated measurement.
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