그림 1. 제안된 위상고정루프. Fig. 1. Proposed PLL.
그림 2. FVC 개수에 따른 개념적인 루프 필터 파형 변화. Fig. 2. Conceptual Loop Filter waveform change according to the number of FVC.
그림 3. (a) 전압제어발진기 지연단. (b) VCR 회로. Fig. 3. (a) VCO delay stage. (b) VCR circuit.
그림 4. (a) FVC 회로도. (b) 제어 신호 타이밍. Fig. 4. (a) FVC circuit. (b) Control signal timing.
그림 5. (a) VLPF와 VFVC1,2,3 시뮬레이션 결과. (b) VLPF 와 VFVC1,2,3 확대 파형. Fig. 5. (a) VLPF and VFVC1,2,3 simulation results. (b) VLPF and VFVC1,2,3 enlarged waveforms.
그림 6. (a) 제안된 위상고정루프의 시뮬레이션 결과. (b) 제안된 위상고정루프에서 FVC를 제거한 시뮬레이션 결과. Fig. 6. (a) Simulation results of proposed PLL (b) Simulation results of without FVC from proposed PLL.
그림 7. 지터 시뮬레이션 (a) 제안된 위상고정루프. (b) 일반적인 위상고정루프. Fig. 7. Jitter simulation (a) proposed PLL. (b) conventional PLL.
참고문헌
- J. Choi, J. Park, W. Kim and J. Laskar, "High multiplication factor capacitor multiplier for an on-chip PLL loop filter," Electronics Letters, vol. 45, no. 5, pp. 239-240, Feb. 2009. https://doi.org/10.1049/el:20092874
- Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, D. Jeong, and W. Kim, "A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 536-542, May 2002. https://doi.org/10.1109/4.997845
- B. Catli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. R. Ahmadi, H. Maarefi, A. Momtaz, and N. Kocaman, "A 2sub-200fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications," in CICC, 2013, pp. 1-4.
- Youn-Gui Song, Young-Shig Choi and Ji-Goo Ryu, "A phase locked loop with resistance and capacitance scaling scheme," IEEK SD, vol. 46, no. 4, pp. 37-44, April 2009.
- L. Liu, T. Sakurai, and M. Takamiya, "A charge-domain auto-and cross- correlation based data synchronization scheme with power-and area-efficient PLL for impulse radio UWB receiver," IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1349-1359, June 2011. https://doi.org/10.1109/JSSC.2011.2128210
- H. J. Kim and Young-Shig Choi, "Increased effective capacitance with current modulator in PLL," IEEK SD, vol. 53, no. 4, pp. 37-44, April 2016.
- Pang-Jung Liu, Chih-Yao Hsu and Yi-Hsiang Chang, "Techniques of Dual-Path Error Amplifier and Capacitor Multiplier for On-Chip Compensation and Soft-Start Function," IEEE Transactions on power electronics, vol. 30, no. 3, pp. 1403-1410, Mar. 2015. https://doi.org/10.1109/TPEL.2014.2320282
- Pengfei Liao, Ping Luo, Weizhong Chen, Bo Zhang, "Embedded Advanced Capacitor Multiplier Compensation for Two-stage Amplifier with Large Capacitive Loads," Communications, Circuits and Systems (ICCCAS), vol. 2, pp. 362-365, Nov. 2013.
- J. Sharma and H. Krishnaswamy, "A dividerless reference-sampling RF PLL with -253.5dBc jitter FOM and -67dBc reference spurs", IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp. 258-259, Feb. 2018.