The Journal of Korea Institute of Information, Electronics, and Communication Technology (한국정보전자통신기술학회논문지)

Korea Information Electronic Communication Technology (한국정보전자통신기술학회)
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An Extremely Small Size Multi-Loop Phase Locked Loop

복수개의 부궤환 루프를 가진 초소형 크기의 위상고정루프

  • Received : 2018.10.16
  • Accepted : 2018.11.14
  • Published : 2019.02.28
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Abstract

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

본 논문에서는 복수개의 부궤환 루프를 도입하여 칩 크기를 획기적으로 줄이면서 잡음 특성을 유지할 수 있는 위상고정루프를 제안하였다. 칩 면적을 최소화하는 것이 주목표이므로 하나의 작은 크기의 커패시터로 구성된 1차 루프필터와 복수개의 FVC를 사용하여 위상고정루프를 설계하였다. 전압제어 발진기에 연결된 복수개의 주파수-전압 변환 회로(frequency voltage converter : FVC)는 위상고정루프 내부에 복수개의 부궤환 루프를 만든다. 제안된 위상고정루프에서는 복수개의 부궤환 루프가 크기가 아주 작은 하나의 커패시터로만 구성된 루프필터를 가진 위상고정루프를 안정하게 동작하도록 해준다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 1.6ps 지터와 $10{\mu}s$ 위상고장시간을 보여주었다.

Keywords

JBJTBH_2019_v12n1_1_f0001.png 이미지

그림 1. 제안된 위상고정루프. Fig. 1. Proposed PLL.

JBJTBH_2019_v12n1_1_f0002.png 이미지

그림 2. FVC 개수에 따른 개념적인 루프 필터 파형 변화. Fig. 2. Conceptual Loop Filter waveform change according to the number of FVC.

JBJTBH_2019_v12n1_1_f0003.png 이미지

그림 3. (a) 전압제어발진기 지연단. (b) VCR 회로. Fig. 3. (a) VCO delay stage. (b) VCR circuit.

JBJTBH_2019_v12n1_1_f0004.png 이미지

그림 4. (a) FVC 회로도. (b) 제어 신호 타이밍. Fig. 4. (a) FVC circuit. (b) Control signal timing.

JBJTBH_2019_v12n1_1_f0005.png 이미지

그림 5. (a) VLPF와 VFVC1,2,3 시뮬레이션 결과. (b) VLPF 와 VFVC1,2,3 확대 파형. Fig. 5. (a) VLPF and VFVC1,2,3 simulation results. (b) VLPF and VFVC1,2,3 enlarged waveforms.

JBJTBH_2019_v12n1_1_f0006.png 이미지

그림 6. (a) 제안된 위상고정루프의 시뮬레이션 결과. (b) 제안된 위상고정루프에서 FVC를 제거한 시뮬레이션 결과. Fig. 6. (a) Simulation results of proposed PLL (b) Simulation results of without FVC from proposed PLL.

JBJTBH_2019_v12n1_1_f0007.png 이미지

그림 7. 지터 시뮬레이션 (a) 제안된 위상고정루프. (b) 일반적인 위상고정루프. Fig. 7. Jitter simulation (a) proposed PLL. (b) conventional PLL.

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