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The Latest Trends and Issues of Anion-based Memristor

음이온 기반 멤리스터의 최신 기술동향 및 이슈

  • Lee, Hong-Sub (Department of Materials Science & Engineering, Kangwon National University)
  • 이홍섭 (강원대학교 재료공학과)
  • Received : 2019.03.01
  • Accepted : 2019.03.28
  • Published : 2019.03.30

Abstract

Recently, memristor (anion-based memristor) is referred to as the fourth circuit element which resistance state can be gradually changed by the electric pulse signals that have been applied to it. And the stored information in a memristor is non-volatile and also the resistance of a memristor can vary, through intermediate states, between high and low resistance states, by tuning the voltage and current. Therefore the memristor can be applied for analogue memory and/or learning device. Usually, memristive behavior is easily observed in the most transition metal oxide system, and it is explained by electrochemical migration motion of anion with electric field, electron scattering and joule heating. This paper reports the latest trends and issues of anion-based memristor.

Keywords

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Fig. 1. Conceptual schematic of resistive switching mechanism of memristor.

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Fig. 2. Typical I-V characteristic of memristor. The numbers indicate switching sequence. (reprinted with permission from [13], Springer Nature).

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Fig. 3. Conceptual schematic of representative resistive switching mechanism of filament type and interface type. Arrows colors of each bias correspond to directions of oxygen anion migration.

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Fig. 4. Complementary switching curve. (reprinted with permission from [16], Springer Nature).

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Fig. 5. a) Schematic diagram of crossbar array architecture, b) circuit diagram of 2 x 2 crossbar array architecture. (reprinted with permission from [19], Springer Nature).

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Fig. 7. Virtual potentiation/depression characteristics: a) ideal curve, b) real curve.

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Fig. 11. Conceptual schematic of gate tunable potentiation/depression curve.

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Fig. 6. Solutions for sneak current issue.

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Fig. 8. a) a representative TEM image of a 3 × 3 memristor crossbar array with 2 × 2nm2 device area and with sub-12-nm pitch. b) a typical I-V curve for a 2-nm Pt/TiOx/HfO2/Pt memristor in the array. c) Simulated electric field distribution in 2-nm memristor crossbars with the centre cell selected are plotted for a cross-sectional view along the bottom electrode direction. (reprinted with permission from [22], Springer Nature).

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Fig. 9. a) a conceptual schematic of the epiRAM during switching. b) cross-sectional TEM image of 60nm SiGe grown on a Si substrate. Scale bar, 25 nm c) cross-sectional SEM image of an epiRAM device. (reprinted with permission from [23], Springer Nature).

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Fig. 10. a) ID-VD curves for ten consecutive sweeps at each gate bias VG for the same device. b) Transfer characteristics of a memtransistor at VD = 0.1 V. (reprinted with permission from [24], Springer Nature).

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