References
- French, M. L., Chen, C. Y., Sathianathan, H., & White, M. H. "Design and scaling of a SONOS multidielectric device for nonvolatile memory applications", IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 17(3), 390-397. (1994). https://doi.org/10.1109/95.311748
- Tanaka, H., Kido, M., Yahashi, K., Oomura, M., Katsumata, R., Kito, M., ... & Iwata, Y. "Bit cost scalable technology with punch and plug process for ultra high density flash memory", In 2007 IEEE Symposium on VLSI Technology pp. 14-15. IEEE. (2007).
- Katsumata, R., Kito, M., Fukuzumi, Y., Kido, M., Tanaka, H., Komori, Y., ... & Zhang, L. "Pipe-shaped BiCS flash memory with 16 stacked layers and multilevel-cell operation for ultra high density storage devices", In 2009 Symposium on VLSI Technology pp. 136-137. IEEE. (2009).
- Jang, J., Kim, H. S., Cho, W., Cho, H., Kim, J., Shim, S. I., ... & Lim, J. S. "Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory", In 2009 Symposium on VLSI Technology pp. 192-193. IEEE. (2009).
- Choi, E. S., & Park, S. K. "Device considerations for high density and highly reliable 3D NAND flash cell in near future", In 2012 International Electron Devices Meeting pp. 9-4. IEEE. (2012).
- Whang, S., Lee, K., Shin, D., Kim, B., Kim, M., Bin, J., ... & Cho, S. "Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application", In 2010 International Electron Devices Meeting pp. 29-7. IEEE. (2010).
- Kim, W., Choi, S., Sung, J., Lee, T., Park, C., Ko, H., ... & Park, Y. "Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage", In 2009 Symposium on VLSI Technology pp. 188-189. IEEE. (2009).
- Ricco, B., Torelli, G., Lanzoni, M., Manstretta, A., Maes, H. E., Montanari, D., & Modelli, A. "Nonvolatile multilevel memories for digital applications", Proceedings of the IEEE, 86(12), 2399-2423. (1998). https://doi.org/10.1109/5.735448
- Bez, R., Camerlenghi, E., Modelli, A., & Visconti, A. "Introduction to flash memory", Proceedings of the IEEE, 91(4), 489-502. (2003). https://doi.org/10.1109/JPROC.2003.811702
- White, M. H., Yang, Y., Purwar, A., & French, M. L. "A low voltage SONOS nonvolatile semiconductor memory technology", IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 20(2), 190-195. (1997). https://doi.org/10.1109/95.588573
- Arreghini, A., Akil, N., Driussi, F., Esseni, D., Selmi, L., & Van Duuren, M. J. "Long term charge retention dynamics of SONOS cells", Solid-State Electronics, 52(9), 1460-1466. (2008). https://doi.org/10.1016/j.sse.2008.04.016
- Chang, J. J. "Theory of MNOS memory transistor", IEEE Transactions on Electron Devices, 24(5), 511-518. (1977). https://doi.org/10.1109/T-ED.1977.18770
- Chiang, T. Y., Chao, T. S., Wu, Y. H., & Yang, W. L. "High-program/erase-speed SONOS with in situ silicon nanocrystals", IEEE Electron Device Letters, 29(10), 1148-1151. (2008). https://doi.org/10.1109/LED.2008.2002944
- Choi, S., Yang, H., Chang, M., Baek, S., Hwang, H., Jeon, S., ... & Kim, C. "Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices", Applied Physics Letters, 86(25), 251901. (2005). https://doi.org/10.1063/1.1951060
- Lim, J. G., Yang, S. D., Yun, H. J., Jung, J. K., Park, J. H., Lim, C., ... & Lee, G. W. "High performance SONOS flash memory with in-situ silicon nanocrystals embedded in silicon nitride charge trapping layer", Solid-State Electronics, 140, 134-138. (2018). https://doi.org/10.1016/j.sse.2017.10.031
- White, M. H. "Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures", Solid-State Electronics, 44(6), 949-958. (2000). https://doi.org/10.1016/S0038-1101(00)00012-5
- Wang, Y., & White, M. H. "An analytical retention model for SONOS nonvolatile memory devices in the excess electron state", Solid-State Electronics, 49(1), 97-107. (2005). https://doi.org/10.1016/j.sse.2004.06.009
- Morokov, Y. N., Novikov, Y. N., Gritsenko, V. A., & Wong, H. "Two-fold coordinated nitrogen atom: an electron trap in MOS devices with silicon oxynitride as the gate dielectric", Microelectronic engineering, 48(1-4), 175-178. (1999). https://doi.org/10.1016/S0167-9317(99)00365-2
- Wong, H., & Gritsenko, V. A. "Defects in silicon oxynitride gate dielectric films", Microelectronics Reliability, 42(4-5), 597-605. (2002). https://doi.org/10.1016/S0026-2714(02)00005-7
- Perera, R., Ikeda, A., Hattori, R., & Kuroki, Y. "Effects of post annealing on removal of defect states in silicon oxynitride films grown by oxidation of silicon substrates nitrided in inductively coupled nitrogen plasma", Thin Solid Films, 423(2), 212-217. (2003). https://doi.org/10.1016/S0040-6090(02)01044-1