Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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Compensation of Neutral Point Deviation under Generalized 3-Phase Imbalance in 3-level NPC

  • Jung, Kyungsub (Department of Electronic Engineering, Chonbuk National University) ;
  • Suh, Yongsug (Department of Electronic Engineering, Chonbuk National University)
  • Received : 2018.03.22
  • Accepted : 2018.08.16
  • Published : 2018.11.20
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Abstract

This paper presents a neutral point deviation and ripple compensation control method for application to 3-level NPC converters. The neutral point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral point of the dc-link. This paper also proposes a control scheme to compensate for the neutral point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the pole voltages and ac input currents are employed to accurately explain the behavior of 3-level NPC converters. Simulation and experimental results are presented to verify the validity of the proposed method.

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References

  1. J. Zarogoza, J. Pou, S. Ceballos, E. Robles, and C. Jaen, “Voltage-balance compensator for a carrier-based modulation in the neutral-point-clamped converter,” IEEE Trans. Ind. Electron., Vol. 56, No. 2, pp. 305-314, Feb. 2009. https://doi.org/10.1109/TIE.2008.2009195
  2. J. Zarogoza, J. Pou, S. Ceballos, E. Robles, P. Ibanez, and J. L. Villate, “A comprehensive study of a hybrid modulation technique for the neutral-point-clamped converter,” IEEE Trans. Ind. Electron., Vol. 56, No. 2, pp. 294-304, Feb. 2009. https://doi.org/10.1109/TIE.2008.2005132
  3. C. Wang and Y. Li, “Analysis and calculation of zerosequence voltage considering neutral-point potential balancing in three-level NPC converter,” IEEE Trans. Ind. Electron., Vol. 57, No. 7, pp. 2262-2271, Jul. 2010. https://doi.org/10.1109/TIE.2009.2024093
  4. C. Wang and Y. Li, “Analysis and calculation of zerosequence voltage considering neutral-point potential balancing in three-level NPC converter,” IEEE Trans. Ind. Electron., Vol. 57, No. 7, pp. 2262-2271, Jul. 2010. https://doi.org/10.1109/TIE.2009.2024093
  5. W. Lixiang, W. Yuliang, L. Chongjian, W. Huiqing, L. Shixiang, and L. Fahai, "A novel space vector control of three-level PWM converter," Proc. IEEE Power Electron. Drive Syst., pp.745-750, 1999.
  6. N. Celanovic and D. Boroyevich, "A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters," IEEE Trans. Power Electron., Vol. 15, No. 2, pp.242-249, Mar. 2000.
  7. K. Yamanaka, A. M. Hava, H. Kirino, Y. Tanaka, N. Koga, and T. Kume, "A novel neutral point potential stabilization technique using the information of output current polarities and voltage vector," in Conf. Rec. IEEE IAS Annu. Meeting, pp. 851-858, 2001.
  8. S. Busquets-Monge, J. D. Ortega, J. Bordonau, J. A. Beristain, and J. Rocabert, “Closed-loop control of a three-phase neutral-point-clamped inverter using an optimized virtual-vector-based pulsewidth modulation,” IEEE Trans. Ind. Electron., Vol. 55, No. 5, pp. 2061-2071, May 2008. https://doi.org/10.1109/TIE.2008.918646
  9. B. Abdul Rahiman, G. Narayanan, and V. T. Ranganathan, “Modified SVPWM method for three level VSI with synchronized and symmetrical waveforms,” IEEE Trans. Ind. Electron., Vol. 54, No. 1, pp. 486-494, Feb. 2007. https://doi.org/10.1109/TIE.2006.888801
  10. Y. Lai, Y. Chou, and S. Pai, "Simple PWM technique of capacitor voltage balance for three-level inverter with dc-link voltage sensor only," in Proc. 33rd Annu. Conf. IEEE IECON, pp. 1749-1754, 2007.
  11. K. H. Bhalodi and P. Agrawal, "Space vector modulation with dc-link voltage balancing control for three-level inverters," in Proc. Int. Conf. PEDES, pp. 1-6, 2006.
  12. J. Suh, C. Choi, and D. Hyun, "A new simplified spacevector PWM method for three-level inverters," in Proc. 14th Annu. APEC, pp. 515-520, 1999.
  13. J. Holtz and N. Oikonomou, "Neutral point potential balancing method at low modulation index for three-level inverter medium voltage drives," in Conf. Rec. IEEE IAS Annu. Meeting, pp. 1246-1252, 2005.
  14. J. Holtz and N. Oikonomou, “Neutral point potential balancing method at low modulation index for three-level inverter medium voltage drives,” IEEE Trans. Ind. Electron., Vol. 43, No. 3, pp. 761-768, May/Jun. 2007.
  15. M. Malinowski, S. Stynski, W. Kolomyjski, and M. P. Kazmierkowski, “Control of three-level PWM converter applied to variable-speed-type turbines,” IEEE Trans. Ind. Electron., Vol. 56, No. 1, pp. 69-77, Jan. 2009. https://doi.org/10.1109/TIE.2008.927245
  16. A. Choudhury and P. Pillay, "Modified DC-bus voltage balancing algorithm for a three-level neutral-point-clamped PMSM inverter drive with reduced commom-mode voltage," IEEE Trans. Ind. Appl., Vol. 52, No. 1, pp. 272-292, Jan./Feb. 2016.
  17. U. Choi, F. Blaabjerg, and K. Lee, “Method to minimize the low-frequency neutral-point voltage oscillations with time-offset injection for neutral-point-clamped inverters,” IEEE Trans. Ind. Appl., Vol. 51, No. 2, pp. 1678-1691, Mar./Apr. 2015. https://doi.org/10.1109/TIA.2014.2350079
  18. S. Ogasawara and H. Akagi, "Analysis of variation of neutral point potential in neutral-point-clamped voltage source PWM inverter," in Conf. Rec. IEEE IAS Annu. Meeting, pp. 965-970, 1993.
  19. S. Qiang, L. Wenhua, Y. Qingguang, X. Xiaorong, and W. Zhonghong, "A neutral-point potential balancing method for three-level NPC inverters using analytically injected zero-sequence voltage," in Proc. IEEE Appl. Power. Electron. Conf., pp. 228-233, 2003.
  20. L. Jun, Q. H. Alex, Q. Zhaoming, and Z. Huijie, "A novel carrier-based PWM method for 3-level NPC inverter utilizing control freedom degree," in Proc. IEEE Power Electron. Spec. Conf., pp. 1899-1904, 2007.
  21. A. Videt, P. Le Moigne, N. Idir, P. Baudesson, and X. Cimetiere, “A new carrier-based PWM providing commonmode- current reduction and dc-bus balancing for threelevel inverters,” IEEE Trans. Ind. Electron., Vol. 54, No. 6, pp. 3001-3011, Dec. 2007. https://doi.org/10.1109/TIE.2007.907001
  22. K. Jung and Y. Suh, "Analysis of neutral point deviation in 3-level NPC converter under unbalanced 3-phase AC grid," IEEE Energy Conversion Congress and Expopsition (ECCE)., pp. 1-8, Sep. 2016.
  23. J. Shen, S. Schroder, B. Duro, and R. Roesner, “A neutralpoint balancing controller for a three-level inverter with full power-factor range and low distortion,” IEEE Trans. Ind. Appl., Vol. 49, No. 1, pp. 138-148, Jan./Feb. 2013. https://doi.org/10.1109/TIA.2012.2228615
  24. A. Choudhury and P. Pillay, “Discontinuous hybrid-PWMbased dc-link voltage balancing algorithm for a three-level neutral-point-clamped (NPC) traction inverter drive,” IEEE Trans. Ind. Appl., Vol. 52, No. 4, pp. 3071-3082, Jul./Aug. 2016. https://doi.org/10.1109/TIA.2016.2533607
  25. "IEEE recommended practice for monitoring electric power quality," IEEE Std 1159-2009 (Revision of IEEE Std 1159-1995), pp. 15, Jun. 2009.
  26. M. Bollen, “Characterisation of voltage sags experienced by three-phase adjustable-speed drives,” IEEE Trans. Power. Del., Vol. 12, No. 4, pp. 1666-1671, Oct. 1997. https://doi.org/10.1109/61.634188
  27. Y. Suh, Y. Go, and D. Roh, “A comparative study on control algorithm for active front-end rectifier of large motor drives under unbalanced input,” IEEE Trans. Ind. Appl., Vol. 47, No. 3, pp. 1419-1431, May/Jun. 2011. https://doi.org/10.1109/TIA.2011.2126015
  28. Y. Suh and A. Lipo, “Control scheme in hybrid synchronous stationary frame for PWM AC/DC converter under generalized unbalanced operating conditions,” IEEE Trans. Ind. Appl., Vol. 42, No. 3, pp. 825-835, May/Jun. 2016.