Acknowledgement
Grant : Numerical simulation to overcome process limitations below 10 nm semiconductor, Plasma enhanced atomic-layer-deposition process and alternatives for gate spacer and multi-patterning technology
Supported by : Korea Research Institute of Standard and Science (KRISS), National Research Council of Science and Technology (NST), MOTIE (Ministry of Trade, Industry & Energy), Ministry of Science, ICT and Future Planning, Korea Institute of Energy Technology Evaluation and Planning (KETEP)
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