Journal of Multimedia Information System

한국멀티미디어학회 (Korea Multimedia Society)
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A Current Compensating Scheme for Improving Phase Noise Characteristic in Phase Locked Loop

  • Han, Dae Hyun (Dept. of Electronic Engineering, Dongeui University)
  • 투고 : 2018.05.17
  • 심사 : 2018.06.22
  • 발행 : 2018.06.30
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초록

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

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참고문헌

  1. Himanshu Arora, Nikolaus Klemmer, James C. Morizio and Patrick D. Wolf, "Enhanced phase noise modeling of fractional-N frequency synthesizers," IEEE Trans. Circuits Syst. I, vol. 52, pp. 379-395, Feb. 2005. https://doi.org/10.1109/TCSI.2004.841594
  2. H. Y. Chang, Y. L. Yeh, Y. C. Liu, M. H. Li, and K. Chen, "A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65-nm CMOS technology," IEEE Transactions on Microwave Theory and Techniques, vol. 62, no. 3, pp. 543-555, Mar. 2014. https://doi.org/10.1109/TMTT.2014.2302747
  3. B. Catli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. R. Ahmadi, H. Maarefi, A. Momtaz, and N. Kocaman, "A sub-200fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications," in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 1-4, Nov. 2013.
  4. Tsung-Hsien Lin and William J. Kaiser, "A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop," IEEE J. Solid-State Circuits, vol. 36, pp. 424-431, March. 2001. https://doi.org/10.1109/4.910481
  5. Hung-Ming Chien, Tsung-Hsien Lin, Brima Ibrahim, Lijun Zhang, Maryam Rofougaran, Ahmadreza Rofougaran and William J. Kaiser, "A 4GHz fractional-N synthesizer for IEEE 802.11a," in Proceeding of the 2004 Symposium on VLSI Circuits Design, pp. 46-49.
  6. G. Jeon, K. K. Kim and Y. B. Kim, "A low jitter PLL design using active loop filter and low-dropout regulator for supply regulation," in Proceeding of the 2015 IEEE International SoC Design Conference, pp. 223-224, Nov. 2015.
  7. G. Blasco, E. Isern, E. Martin, "Design of a stable pulse generator system based on a Ring-VCO Phase-Locked Loop using 180nm CMOS technology," in Proceeding of the 2015 IEEE Design of Circuits and Integrated Systems (DCIS), pp.1-6, Nov. 2015
  8. Ching-Yuan Yang and Shen-Iuan Liu, "Fast-switching frequency synthesizer with a discriminator-aided phase detector," IEEE J. Solid-State Circuits, vol. 35, pp. 1445-1452, October. 2000. https://doi.org/10.1109/4.871321