마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제25권1호
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  • Pages.1-10
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  • 2018
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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봉지막이 박형 실리콘 칩의 파괴에 미치는 영향에 대한 수치해석 연구

Effects of Encapsulation Layer on Center Crack and Fracture of Thin Silicon Chip using Numerical Analysis

  • 좌성훈 (서울과학기술대학교 NID융합대학원) ;
  • 장영문 (서울과학기술대학교 일반대학원) ;
  • 이행수 (울산과학대학교 기계공학부)
  • Choa, Sung-Hoon (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology) ;
  • Jang, Young-Moon (Dept. Of Manufacturing System and Design Engineering, Seoul National University of Science and Technology) ;
  • Lee, Haeng-Soo (Department of Mechanical Engineering, Ulsan College)
  • 투고 : 2017.12.01
  • 심사 : 2018.03.19
  • 발행 : 2018.03.31
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초록

최근 플렉서블 OLED, 플렉서블 반도체, 플렉서블 태양전지와 같은 유연전자소자의 개발이 각광을 받고 있다. 유연소자에 밀봉 혹은 봉지(encapsulation) 기술이 매우 필요하며, 봉지 기술은 유연소자의 응력을 완화시키거나, 산소나 습기에 노출되는 것을 방지하기 위해 적용된다. 본 연구는 봉지막(encapsulation layer)이 반도체 칩의 내구성에 미치는 영향을 고찰하였다. 특히 다층 구조 패키지의 칩의 파괴성능에 미치는 영향을 칩의 center crack에 대한 파괴해석을 통하여 살펴보았다. 다층구조 패키지는 폭이 넓어 칩 위로만 봉지막이 덮고있는 "wide chip"과 칩의 폭이 좁아 봉지막이 칩과 기판을 모두 감싸고 있는 "narrow chip"의 모델로 구분하였다. Wide chip모델의 경우 작용하는 하중조건에 상관없이 봉지막의 두께가 두꺼울수록, 강성이 커질수록 칩의 파괴성능은 향상된다. 그러나 narrow chip모델에 인장이 작용할 때 봉지막의 두께가 두껍고 강성이 커질수록 파괴성능은 악화되는데 이는 외부하중이 바로 칩에 작용하지 않고 봉지막을 통하여 전달되기에 봉지막이 강하면 강한 외력이 칩내의 균열에 작용하기 때문이다. Narrow chip모델에 굽힘이 작용할 경우는 봉지막의 강성과 두께에 따라 균열에 미치는 영향이 달라지는데 봉지막의 두께가 작을 때는 봉지막이 없을 때보다 파괴성능이 나쁘지만 강성과 두께의 증가하면neutral axis가 점점 상승하여 균열이 있는 칩이 neutral axis에 가까워지게 되므로 균열에 작용하는 하중의 크기가 급격히 줄어들게 되어 파괴성능은 향상된다. 본 연구는 봉지막이 있는 다층 패키지 구조에 다양한 형태의 하중이 작용할 때 패키지의 파괴성능을 향상시키기 위한 봉지막의 설계가이드로 활용될 수 있다.

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

키워드

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