전기전자학회논문지 (Journal of IKEEE)

  • 제22권1호
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  • Pages.98-103
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  • 2018
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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CNTFET 기반 회로 설계를 위한 공정 편차 분석에 관한 연구

A Study on the Process Variation Analysis for CNTFET-based Circuit Design

  • Cho, Geunho (Dept. of Electronics Engineering, Seokyeong University)
  • 투고 : 2017.12.28
  • 심사 : 2018.03.28
  • 발행 : 2018.03.31
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초록

차세대 반도체로 각광받고 있는 CNTFET은 기존 MOSFET의 Source와 Drain 사이에 CNT를 배치하여 그 성능을 향상시킬 수 있는 구조를 가지고 있으나, 다양한 CNT 배치로 인한 CNTFET의 구조적 변화는 소자 성능에 대한 해석의 복잡도를 증가시켜, 공정 편차가 반도체 소자 성능에 미치는 영향을 분석하고자 할 때, 기존의 MOSFET에 비해 보다 많은 계산을 요구하는 문제점을 가지고 있다. 이러한 문제점은 공정편차 분석에 필요한 시뮬레이션 시간을 급격하게 증가시키고 기존 툴(tool)로 분석할 수 없는 경우를 포함하고 있어 CNTFET으로 회로를 디자인 하는데 중요한 걸림돌로 작용하고 있다. 본 연구에서는 시뮬레이션의 급격한 증가를 해결하기 위한 방법으로서 기존 Linear Programming이 활용될 수 있음을 보이고 그 효과에 대해 자세히 논의하고자 한다. 시뮬레이션 결과 CNT 최대 배치수가 6에서 12까지 증가할 때, Linear Programming 방법은 시뮬레이션 횟수를 약 2.5배 감소시킬 수 있음을 보이고 있다.

The CNTFET, which is widely recognized as a next-generation semiconductor, has a structure that can improve performance by positioning CNTs between the source and drain of a conventional MOSFET. However, positioning CNTs increases the complexity of a CNTFET's structure, and the process variation changes the complex structure into various shapes; so, when CNTFET device performance is analyzed, it requires more computation than that of a conventional MOSFET. These problems greatly increase the simulation time necessary for the analysis, and sometimes that analysis cannot be performed using an existing tool; they are therefore important obstacles to designing a circuit using a CNTFET. In this study, we will show that the existing Linear Programming methodology can be utilized to solve the long simulation time problem and discuss the effect of the suggested method in detail. Simulation results show that the Linear Programming method can reduce the number of simulation about 2.5 times when the maximum number of CNT is changed from 6 to 12.

키워드

참고문헌

  1. P. R. Yasasvi Gangavarapu., et al. "Graphene Electrodes as Barrier-Free Contacts for Carbon Nanotube Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 64, pp. 4335-4339, 2017. DOI: 10.1109/TED.2017.2741061
  2. J. Deng, et al., "A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part I: Model of the Intrinsic Channel Region," IEEE Transactions on Electron Devices, vol 54, pp. 3186-3194, 2007. DOI: 10.1109/TED.2007.909030
  3. J. Deng, et al., "A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its application-Part II: Full device model and circuit performance benchmarking," IEEE Transactions on Electron Devices, vol. 54, pp. 3195-3205, 2007. DOI: 10.1109/TED.2007.909043
  4. J. Zhang, et al., "Carbon nanotube robust digital VLSI," EEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 31, no. 4, pp. 453-471, 2012. DOI: 10.1109/TCAD.2012.2187527
  5. Patil N, et al., "Design methods for misaligned and mispositioned carbon nanotube immune circuits," IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, vol. 27, pp. 1725-1736, 2008. DOI: 10.1109/TCAD.2008.2003278
  6. B. Byeon, et al., "Bio-fabrication of nanomesh channels of single-walled carbon nanotubes for locally gated field-effect transistors," Nanotechnology, vol. 28, pp. 025304-1-025304-9, 2017. DOI:10.1088/1361-6528/28/2/025304
  7. D. Lee, et al., "Three-Dimensional Fin Structured Semiconducting Carbon Nanotube Network Transistor," ACS Nano, vol 10, pp. 20894-10900, 2016. DOI: 10.1021/acsnano.6b05429
  8. G. Cho, et al., "Modeling Undeposited CNTs for CNTFET Operation," IEEE Transactions on Device and Materials Reliability, " vol. 11, pp. 263 - 272, 2011. DOI: 10.1109/TDMR.2011.2123896
  9. G. Cho, et al., "On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment," Journal of Electronic Testing-Theory and Applications, vol. 29, pp. 261-273, 2013. DOI: 10.1007/s10836-013-5388-6
  10. G. Cho, et al., "Circuit-Level Simulation of a CNTFET with Unevenly Positioned CNTs by Linear Programming," IEEE Transactions on Device and Materials Reliability, vol. 14, pp. 1-10, 2014. DOI: 10.1109/TDMR.2013.2279154