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Development Process of FPGA-based Departure from Nucleate Boiling Ratio Algorithm Using Systems Engineering Approach

  • Hwang, In Sok (Department of NPP Engineering, KEPCO International Nuclear Graduate School) ;
  • Jung, Jae Cheon (Department of NPP Engineering, KEPCO International Nuclear Graduate School)
  • Received : 2018.11.08
  • Accepted : 2018.12.27
  • Published : 2018.12.31

Abstract

This paper describes the systems engineering development process for the Departure from Nucleate Boiling Ratio (DNBR) algorithm using FPGA. Current Core Protection Calculator System (CPCS) requirement and DNBR logic are analyzed in the reverse engineering phase and the new FPGA based DNBR algorithm is designed in the re-engineering phase. FPGA based DNBR algorithm is developed by VHSIC Hardware Description Language (VHDL) in the implementation phase and VHDL DNBR software is verified in the software Verification & Validation phase. Test cases are developed to perform the software module test for VHDL software modules. The APR 1400 simulator is used to collect the inputs data in 100%, 75%, and 50% reactor power condition. Test input signals are injected to the software modules following test case tables and output signals are compared with the expected test value. Minimum DNBR value from developed DNBR algorithm is validated by KEPCO E&C CPCS development facility. This paper summarizes the process to develop the FPGA-based DNBR calculation algorithm using systems engineering approach.

Keywords

HSSTBN_2018_v14n2_41_f0001.png 이미지

[Figure 1] Vee model for FPGA-based CPCS DNBR algorithm

HSSTBN_2018_v14n2_41_f0002.png 이미지

[Figure 2] WBS Structure

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[Figure 3] Functional architecture

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[Figure 4] EFFBD of Module 4

Software module test case

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Comparison minimum DNBR with KEPCO E&C facility

HSSTBN_2018_v14n2_41_t0002.png 이미지

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