그림 1. 설계된 캐스코드 혼합기 회로도 Fig. 1. Schematic of the designed cascode mixer
그림 2. 캐스코드 FET의 I-V 특성 (Vgs2 에 따른 FET2의 동작 점 변화) Fig. 2. I-V characteristics of cascoded FETs (variation of bias point of FET2 according to Vgs2)
그림 4. 설계된 혼합기의 시뮬레이션 결과: (a) RF 주파수에 따른 변환이득, (b) RF 전력에 따른 변환이득, (c) LO, RF 포트에서의 반사 손실 Fig. 4. Simulation results of the designed mixer: (a) conversion gain according to RF frequency, (b) conversion gain according to RF power, and (c) return losses at LO and RF ports
그림 5. 제작된 혼합기의 사진 Fig. 5. The photograph of the fabricated cascode mixer
그림 6. 혼합기의 측정셋업 Fig. 6. Measurement setup of the fabricated mixer
그림 7. 제작된 혼합기의 측정결과: (a) RF 주파수에 따른 변환이득, (b) RF 전력에 따른 변환이득, (c) LO 전력에 따른 변환이득 Fig. 7. Measurement results of the fabricated mixer: (a) conversion gain according to RF frequency, (b) conversion gain according to RF power, and (c) conversion gain according to LO power
그림 3. (a) 출력정합회로, (b) IF 주파수에서의 변환이득의 로드-풀 시뮬레이션(점선)와 정합회로의 출력임피던스(실선) Fig. 3. (a) Schematic of output matching network, (b) load-pull simulation of conversion gain (slotted lines) and output impedance of the designed output matching network (solid line) at IF
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