AES 암호 알고리즘을 위한 고속 8-비트 구조 설계

High-speed Design of 8-bit Architecture of AES Encryption

  • 이제훈 (강원대학교 전자정보통신공학부) ;
  • 임덕규 (강원대학교 전자정보통신공학부)
  • 투고 : 2017.05.26
  • 심사 : 2017.06.30
  • 발행 : 2017.06.30

초록

본 논문은 새로운 8-비트 AES (advanced encryption standard) 암호회로 설계를 제안한다. 대부분 8-비트 AES 암호회로는 성능을 희생시켜 하드웨어 크기를 줄인다. 제안한 AES는 2개의 분리된 S-box들을 갖고, 라운드 연산과 키 생성을 병렬로 연산함으로써, 고속 암호 연산이 가능하다. 제안된 AES 구조의 동작 실험 결과, 제안된 AES-128 구조의 최대 연산 지연은 13.0ns의 크기를 갖고, 77MHz의 최대 동작 주파수로 동작함을 확인하였다. 제안된 AES 구조의 성능은 15.2Mbps가 된다. 결론적으로, 제안된 AES의 성능은 기존 8-비트 AES 구조에 비해 1.54배 향상된 성능을 갖고, 회로크기 증가는 1.17배 증가로 제한된다. 제안된 8비트 구조의 AES-128은 8비트 연산 구조 채택에 따른 성능 감소를 줄이면서 저면적 회로로 구현된다. 제안된 8비트 AES는 고속 동작이 필요한 IoT 어플리케이션에 활용될 것으로 기대된다.

This paper presents new 8-bit implementation of AES. Most typical 8-bit AES designs are to reduce the circuit area by sacrificing its throughput. The presented AES architecture employs two separated S-box to perform round operation and key generation in parallel. From the simulation results of the proposed AES-128, the maximum critical path delay is 13.0ns. It can be operated in 77MHz and the throughput is 15.2 Mbps. Consequently, the throughput of the proposed AES has 1.54 times higher throughput than the other counterpart although the area increasement is limited in 1.17 times. The proposed AES design enables very low-area design without sacrificing its performance. Thereby, it can be suitable for the various IoT applications that need high speed communication.

키워드

참고문헌

  1. A. Lee, "NIST Special Publication 800-21, Guideline for implementing cryptography in the Federal Government National Institute of Standards and Technology", 1999.
  2. P. Shastry, A. Kulkarni, and M. Sutaone, "ASIC implementation of AES." Proc. of INDICON 2012, pp. 1255-1259, Dec. 2012.
  3. P. Ghewari, J. Patil, and A. Chougule, "Efficient hardware design and implementation of AES cryptosystem," Int'l J. of Engineering Science and Technology, vol. 2, no. 3, pp. 213-219, Mar. 2010.
  4. S. M. Farhan, S. A. Khan, and H. Jamal, "An 8-bit systolic AES architecture for moderate data rate applications," Microprocessors and Microsystems, vol. 33, no. 3, pp. 221-231, Mar. 2009. https://doi.org/10.1016/j.micpro.2009.02.013
  5. T. Good and M. Benaissa. "AES on FPGA from the fastest to the smallest," Proc. of CHES 2005, pp. 427-440, 2005.
  6. P. Hamalainen, M. Hannikainen, and T. Hamalainen, "Efficient hardware implementation of security processing for IEEE 802.15.4 wireless networks," Proc. of MWSCAS 2005, pp. 484-487, 2005.
  7. P. Hamalainen, T. Alho, M. Hannikainen, and T. Hamalainen, "Design and implementation of low-area and low-power AES encryption hardware core," Proc. of DSD'06, pp. 577-583, 2006.
  8. M. Feldhofer, S. Dominikus, and J. Wolkerstorfer, "Strong authentication for RFID systems using the AES algorithm," Proc. of CHES'04, pp. 357-370, 2004.
  9. M. Feldhofer, J. Wolkerstorfer, and V.Rijmen. "AES implementation on grain of sand," IEE Proc. of Information Security, vo. 152, no. 1, pp. 13-20, 2005. https://doi.org/10.1049/ip-ifs:20055006
  10. A. Satoh, S, Morioka, K, Takano, and S. Munetoh, "'A compact Rijndael hardware architecture with S-Box optimization," Proc. of ASIACRYPT 2001, vol. 2248, pp. 239-254, Dec. 2001.
  11. J. Chu and M. Benaissa, "Low area memory-free FPGA implementation of the AES algorithm," Proc. of FPL 2012, pp. 623-626, Aug. 2012.
  12. N. Pramstaller, S. Mangard, S. Dominikus, and J. Wolkerstorfer, "Efficient AES implementations on ASICs and FPGAs," Proc of AES 2004, vol. 3373, pp. 98-112, May 2005.
  13. S. Chawla, S. Aggarwal, S. Kamal, and N. Goel, "FPGA implementation of an optimized 8-bit AES architecture: A masked S-Box and pipelined approach," Proc. of CONECCT2015, pp. 1-6, Jul. 2015.
  14. X. Zhang, H. Li, S. Yang, and S. Han, "On a high-performance and balanced method of hardware implementation for AES," Proc. of IEEE Int'l Conf. on SERE-C, pp. 16-20, Jun. 2013.
  15. X. Cai, R. Sun, and J. Liu, "An ultrahigh speed AES processor method based on FPGA," Proc. of INCoS, pp. 633-636, Sep. 2013.