JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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The Effect of Inhibitors on the Electrochemical Deposition of Copper Through-silicon Via and its CMP Process Optimization

  • Lin, Paul-Chang (State Key Laboratory of ASIC and System, School of Microelectronic, Fudan University) ;
  • Xu, Jin-Hai (Semiconductor Manufacturing International Corporation) ;
  • Lu, Hong-Liang (State Key Laboratory of ASIC and System, School of Microelectronic, Fudan University) ;
  • Zhang, David Wei (State Key Laboratory of ASIC and System, School of Microelectronic, Fudan University) ;
  • Li, Pei (Semiconductor Manufacturing International Corporation)
  • Received : 2016.03.07
  • Accepted : 2016.11.05
  • Published : 2017.06.30
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Abstract

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.

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References

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