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나노 공정 시대의 아날로그 반도체 기술

  • 유창식 (한양대학교 융합전자공학부)
  • Published : 2017.01.25
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References

  1. H. Iwai, "Roadmap for 22 nm and beyond," Microelectronic Engineering, vol. 86, no. 7-9, pp. 1520-1528, Sep. 2009. https://doi.org/10.1016/j.mee.2009.03.129
  2. T. Mogami, "CMOS scaling and variability," WIMNACT WS & IEEE EDS Mini-Colloquium on Nano-CMOS Technology, Jan. 2012.
  3. L. L. Lewyn, T. Ytterdal, C. Wulff, and K. Martin, "Analog circuit design in nanoscale CMOS technologies," Proc. IEEE, vol. 97, no. 10, pp. 1687-1714, Oct. 2009. https://doi.org/10.1109/JPROC.2009.2024663
  4. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989. https://doi.org/10.1109/JSSC.1989.572629
  5. P. R. Kinget, "Device mismatch and tradeoffs in the design of analog circuits," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1212-1224, Jun. 2005. https://doi.org/10.1109/JSSC.2005.848021
  6. B. Gilbert, "Current mode, voltage mode, or free mode? A few sage suggestion," Analog Integrated Circuits and Signal Processing, vol. 38, pp. 83-101, 2004. https://doi.org/10.1023/B:ALOG.0000011161.44537.da
  7. R. B. Staszewski, J. L. Wallberg, S. Rezeq, et al., "All-digital PLL and transmitter for mobile phones," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469-2482, Dec. 2005. https://doi.org/10.1109/JSSC.2005.857417
  8. A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, "A 9.4- ENOB 1-V 3.8-mW 100-kS/s SAR ADC with time-domain comparator," Dig. Tech. Papers, IEEE Int. Solid-State Circuits Conf. pp. 246-247, 2008.
  9. Y. Kim and C. Yoo, "A 100-kS/s 8.3-ENOB 1.7-mW timedomain analog-to-digital converter," IEEE Trans. Circuits and Systems-II, vol. 61, no. 6, pp. 408-412, Jun. 2014.
  10. J. Jin, Y. Gao, and E. Sanchez-Sinencio, "An energy efficient time-domain asynchronous 2-b/step SAR ADC with a hybrid R-2R/C-3C DAC structure," IEEE J. Solid-State Circuits, vol. 49, no. 6, pp. 1383-1396, Apr. 2014. https://doi.org/10.1109/JSSC.2014.2317139
  11. M. Park and M. H. Perrott, "A 79 dB SNDR 87 mW 27 MHz bandwidth continuous-time DS ADC with VCO-based integrator and quantizer implemented in 0.13 mm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3344-3358, Dec. 2009. https://doi.org/10.1109/JSSC.2009.2032703
  12. J. Roberts, "Picture coding using pseudo-random noise," IRE Trans. Information Theory, vol. 8, pp. 145-154, Jan. 1962. https://doi.org/10.1109/TIT.1962.1057702
  13. W. Chou and R. M. Gray, "Dithering and its effects on sigmadelta and multistage sigma-delta modulation," IEEE Trans. Information Theory, vol. 37, no. 3, pp. 500-513, May, 1991. https://doi.org/10.1109/18.79906
  14. L. Gammaitoni, P. Hanggi, P. Jung, and F. Marchesoni, "Stochastic resonance," Rev. Modern Physics, vol. 70, no. 1, pp. 223-287, 1998. https://doi.org/10.1103/RevModPhys.70.223
  15. C. Kreucher, K. Kastella, and A. O. Hero, "Information based sensor management for multitarget tracking," Proceedings of SPIE, vol. 2504, pp. 480-489, 2003.
  16. A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207-1215, Dec. 1993. https://doi.org/10.1109/4.261994
  17. S.-H. Lee and B.-S. Song, "A code-error calibrated twostep A/D converter," Dig. Tech. Papers, IEEE Int. Solid-State Circuits Conf. pp. 38-39, 1992.
  18. F. Maloberti, Analog design for CMOS VLSI systems, Springer, Oct. 2001.
  19. O. Ibe, Fundamentals of applied probability and random processes, Elsevier Academic Press, Nov. 2005.
  20. D. McDonnell, N. G. Stocks, C. E. M. Pearce, and D. Abbott, "Analog to digital conversion using suprathreshold stochastic resonance," Proceedings of SPIE, vol. 5649, pp. 75-84, 2005.
  21. Y. Kim, M.-K. Jeon, and C. Yoo, "Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control," Proc. IEEE Int. Symp. Integrated Circuits, pp. 79-82, 2014.