참고문헌
- H. Tanaka, et al, "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory," IEEE Symposium on VLSI Technology, 12-14, pp.14-15, Jun., 2007.
- J. Jang, et al, "Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory," IEEE Symposium on VLSI Technology, 16-18, pp.192-193, Jun., 2009.
- J.-G. Yun, et al, "Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory," IEEE Tansactions on Electron Devices, Vol.58, No.4, pp.1006-1014, Apr., 2011. https://doi.org/10.1109/TED.2011.2107557
- Y. Kim, et al, "Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array," IEEE Electron Device Letters, Vol.34, No.8, pp.990-992, Aug., 2013. https://doi.org/10.1109/LED.2013.2262174
- S. H. Park, et al, "Vertical-Channel STacked ARray (VCSTAR) for 3D NAND flash memory," Solid-State Electronics, Vol.78, pp.34-38, Dec., 2012. https://doi.org/10.1016/j.sse.2012.05.031
- D.-B. Kim, et al, "Investigation of Three Dimensional NAND Flash Memory Based on Gate STacked ARray (GSTAR)," Silicon Nanoelectronics Workshop, 9-10, pp.5-6, Jun., 2013.
- M.-H. Baek, et al, "Comparison of Gate STacked ARray (GSTAR) with Arch and Ultra-Thin Body (UTB) Structured Single Cell," The 29th International Technical Conference on Circuit/Systems Computers and Communications (ITC-CSCC), 1-4, pp.121-123, Jul., 2014.
- A. C. Westerheim, et al, "Substrate bias effects in high-aspect-ratio SiO2 contact etching using an inductively coupled plasma reactor," Journal of Vacuum Science & Technology A, Vol.13, No.3, pp.853-858, May, 1995. https://doi.org/10.1116/1.579841
- C. Liu and B. A.-Shrauner, "Plasma-Etching Profile Model for SiO2 Contact Holes," IEEE Transactions on Plasma Science, Vol.30, No.4, pp.1579-1586, Aug., 2002. https://doi.org/10.1109/TPS.2002.804166
- R. Li, et al, "Continuous deep reactive ion etching of tapered via holes for three-dimensional integration," Journal of Micromechanics and Microengineering, Vol.18, No.12, p.125023, Nov., 2008. https://doi.org/10.1088/0960-1317/18/12/125023
- W. Kim, et al, "Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance," IEEE Electron Device Letters, Vol.31, No.12, pp. 1374-1376, Dec., 2010. https://doi.org/10.1109/LED.2010.2074180
- J. H. Lee, et al, "Investigation of Field Concentration Effects in Arch Gate Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory," Japanese Journal of Applied Physics, Vol.49, No.11, pp.1142021-1142026, Nov., 2010.
- Y.-H. Hsiao, et al, "A Critical Examination of 3D Stackable NAND Flash Memory Architectures by Simulation Study of the Scaling Capability," IEEE International Memory Workshop, 16-19, pp.1-4, May, 2010.
- J. Fu, et al, "Polycrystalline Si Nanowire SONOS Nonvolatile Memory Cell Fabricated on a Gate-All-Around (GAA) Channel Architecture," IEEE Electron Device Letters, Vol.30, No.3, pp.246-249, Mar., 2009. https://doi.org/10.1109/LED.2008.2011503