Journal of Power Electronics

  • 제17권1호
  • /
  • Pages.262-271
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  • 2017
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  • 1598-2092(pISSN)
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  • 2093-4718(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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Performance Analysis of Three-Phase Phase-Locked Loops for Distorted and Unbalanced Grids

  • Li, Kai (School of Automation Engineering, University of Electronic Science and Technology of China) ;
  • Bo, An (School of Automation Engineering, University of Electronic Science and Technology of China) ;
  • Zheng, Hong (School of Automation Engineering, University of Electronic Science and Technology of China) ;
  • Sun, Ningbo (Jinan Huizhi Electric Power Technology Co., Ltd.)
  • 투고 : 2016.04.19
  • 심사 : 2016.09.07
  • 발행 : 2017.01.20
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초록

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

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참고문헌

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피인용 문헌

  1. Benchmarking simulation and theory of various PLLs produce orthogonal signals under abnormal electric grid conditions pp.1432-0487, 2017, https://doi.org/10.1007/s00202-017-0660-x