참고문헌
- J. Rivoir, "Parallel Test Reduces Cost of Test More Effectively Than Just a Cheap Tester", IEEE/SEMI Int'l Electronics Manufacturing Technology Symposium, July, 2004.
- M. Huebner, "Highest Parallel Test for DRAM Enabled through Advanced TRE", IEEE SW Test Workshop, June, 2009.
- K. Eom, D. Han, Y. Lee, H. Kim, S. Kang, "Efficient Multi-site Testing Using ATE Channel Sharing", Journal of Semiconductor Technology and Science., vol 13, June, 2013.
- The International Technology Roadmap for Semiconductors: Test and Test Equipment Section..
- F. C. Gale, "Productivity Factors in Measurement Technology", IEEE Trans. Instrumentation and Measurement., vol 33, no. 3, pp. 177-180, Sep.,1984. https://doi.org/10.1109/TIM.1984.4315196
- H.J. Kim, J.K. Yu, J. Kim, J.B. Oh, H.D. Lim, W. Nah, "Prediction of Signal Transfer Characteristic of Probe Card Using Electro-Magnetic Solvers", IEEE Int'l symposium on Antenna, Propagation and EM theory, Nov., 2008.
- D.Y. Kim, J. Byun, S.H. Lee, S.J. Oh, K.S. Kang, H.Y. Lee, "Signal Integrity Improvements of a MEMS Probe Card Using Back-Drilling and Equalizing Techniques", IEEE Trans. Instrumentation and Measurement., vol 60, no. 3, pp. 872-879, March, 2011. https://doi.org/10.1109/TIM.2009.2036343
- I. Hitoshi, N. Atshshi, I. Naoka, O. Kotaro, "Cantilever Type Probe Card for At-Speed Memory Test on Wafer", IEEE VLSI Test Symposium, May, 2005
- G.Y. Kim, E.J. Byun, K.S. Kang, Y.H. Jun, B.S. Kong, "Wafer-Level Chacterization of Probecards using NAC Probing", IEEE International Test Conference, 2008
- J.H. Lee, B.H. Jo, "A Comparison of Scrub Marks & Contact Resistance Between Cantilever Type and New MEMS Type Probe Cards", IEEE SW Test Workshop, June, 2003
- T. Homorodi, R. Martin, "High Parallelism Memory Test Advances based on MicroSpring Contact Technology", IEEE SW Test Workshop, June, 2001
- B.H. Kim, J.B. Kim, J.H. Kim, "A Highly Manufacturable Large Area Array MEMS Probe Card Using Electroplating and Flipchip Bonding", IEEE Trans. Ind. Electron., vol 56, no. 4, pp. 1079-1085, April, 2009 https://doi.org/10.1109/TIE.2008.2003366
- M. Huebner, "Highest Parallel Test for DRAM Enabled through Advanced TRE", IEEE SW Test Workshop, June, 2009
- Y.H. Liu, N. Kawamata, K. Taoka, "High Throughput Challenges for 300mm Wafer Testing", IEEE SW Test Workshop, 2003
- M. Sindhadevi, M. Kanagasabai, H. Arun, A. K. Shrivastav, "Signal Integrity Analysis of High Speed Interconnects In PCB Embedded with EBG Structures", Journal of Electrical Engineering & Technology, vol 10, Jan. 2015
- C. A. Miller, M. E. Chraft, R. J. Henson, "Intelligent Probe Card Architecture", U.S. Patent 7307433, Dec., 2007
- H. Lee, T. Itoh, "Isolation Circuits Based on Metamaterial Transmission Lines for Multiplexers", Journal of Electromagnetic Engineering and Science, vol 13, Sep. 2013
- H. Johnson and M. Graham, "High-Speed Signal Propagation, Advanced Black Magic", Prentice Hall, 2003