참고문헌
- John L. Henning. "SPEC CPU2006 Benchmark Descriptions" ACM SIGARCH Computer Architecture News, vol.34, no.4, pp.1-17, September 2005.
- JEDEC, DDR4 SDRAM Specification, 2012.
- T. Vogelsang, "Understanding the Energy Consumption of Dynamic Random Access Memories," in MICRO, Dec 2010.
- M. Hashimoto et al., "An Embedded DRAM Module using a Dual Sense Amplifier Architecture in a Logic Process," in ISSCC, Feb 1997.
- Micron Technology Inc., RLDRAM3 Datasheet, 2011.
- P. N. Glaskowsky, "MoSys Explains 1T-SRAM Technology," Microprocessor Report, Sep. 1999.
- Y. Sato et al., "Fast Cycle RAM (FCRAM); a 20-ns Random Row Access, Pipelined Operating DRAM," in VLSI, Jun 1998
- Y. H. Son et al., "Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations," ISCA, 2013.
- Y. H. Son et al., "SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture," CAL, 2016.
- B. Keeth et al., DRAM Circuit Design, 2nd ed. IEEE, 2008.
- A. N. Udipi et al., "Rethinking DRAM Design and Organization for Energy-constrained Multi-cores," ISCA, Jun 2010.
- E. Cooper-Balis et al., "Fine-Grained Activation for Power Reduction in DRAM," IEEE Micro, vol. 30, no 3, 2010.
- Zhang, Tao, et al. "Half-DRAM: a High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation." ISCA, 2014.
- Y. Kim et al., "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM," ISCA, Jun 2012.
- Y. H. Son et al. "Microbank: architecting through-silicon interposer-based main memory systems." SC, 2014.
- J. Ahn et al., "Improving System Energy Efficiency with Memory Rank Subsetting," ACM TACO, vol. 9, no. 1, 2012.
- H. Zheng et al., "Mini-Rank Adaptive DRAM Architecture for Improving Memory Power Efficiency," in MICRO, Nov 2008.
- D. H. Yoon et al., "BOOM: Enabling Mobile Memory Based Low-Power Server DIMMs," in ISCA, Jun 2012.
- D. H. Yoon et al., "Virtualized ECC: Flexible Reliability in Main Memory," IEEE Micro, vol. 31, no. 1, 2011.
- B. Ganesh et al., "Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling," in HPCA, Feb 2007.
- Z. Zhang et al., "Cached DRAM for ILP Processor Memory Access Latency Reduction," IEEE Micro, vol. 21, no. 4, 2001.
- "Virtual Channel DRAM. Elpida Memory, Inc." http://www.elpida.com/en/products/eollvcdram.html.
- D. Lee et al., "Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture," in HPCA, Feb 2013.
- S. Rixner et al., "Memory Access Scheduling," in ISCA, Jun 2000.
- O. Mutlu et al., "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems," in ISCA, Jun 2008.
- Y. Kim et al., "ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers." in HPCA, 2010.
- Y. Kim et al., "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior," in MICRO, Dec 2010.
- E. Ipek et al., "Self-Optimizing Memory Controllers: A Reinforcement Learning Approach," in ISCA, Jun 2008.
- D. Kaseridis et al., "Minimalist Open-page: a DRAM Page-mode Scheduling Policy for the Many-core Era," in MICRO, Dec 2011.
- J. L. Henning, "SPEC CPU2006 Memory Footprint," Computer Architecture News, vol. 35, no. 1, 2007.
- N. Madan et al., "Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy," in HPCA, Feb 2009.
- G. H. Loh et al., "Efficiently Enabling Conventional Block Sizes for Very Large Die-stacked DRAM Caches," in MICRO, Dec 2011.
- J.-S. K.im et al., "A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4x 128 I/Os using TSV-based stacking," in ISSCC, Feb 2011.
- J. T. Pawlowski, "Hybrid Memory Cube," in Hot Chips, Aug 2011.
- A. N. Udipi et al., "Combining Memory and a Controller with Photonics through 3D-stacking to Enable Scalable and Energy-efficient Systems," in ISCA, Jun 2011.
- G. H. Loh, "A Register-file Approach for Row Buffer Caches in Die-stacked DRAMs," in MICRO, Dec 2011.
- Young Hoon Son et al., "Row-buffer decoupling: a case for low-latency DRAM microarchitecture." ISCA, 2014.