JSTS:Journal of Semiconductor Technology and Science

  • 제16권4호
  • /
  • Pages.520-527
  • /
  • 2016
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

A High-Resolution Dual-Loop Digital DLL

  • Kim, Jongsun (Electronic and Electrical Engineering, Hongik University) ;
  • Han, Sang-woo (Electronic and Electrical Engineering, Hongik University)
  • 투고 : 2016.01.02
  • 심사 : 2016.02.29
  • 발행 : 2016.08.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

키워드

참고문헌

  1. Y. Moon, J. Choi, K. Lee, D. Jeong, M. Kim, "An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance," IEEE J. Solid-State Circuits, vol. 35, No. 3, pp. 377-384, 2000. https://doi.org/10.1109/4.826820
  2. S. Bae, H. Chi, Y. Sohn, H. Park, "A VCDL-based 60-760MHz dual-loop DLL with infinite phaseshift capability and adaptive-bandwidth scheme," IEEE J. Solid-State Circuits, vol. 40, No. 5, 2005, pp. 1119-1129. https://doi.org/10.1109/JSSC.2005.845989
  3. R. Yang, S. Liu, "A 40-550MHz harmonic-free all- Digital delay-locked loop using a variable SAR algorithm," IEEE J. Solid-State Circuits, vol. 42, No. 2, Feb 2007, pp. 361-373. https://doi.org/10.1109/JSSC.2006.889381
  4. T. Matano, et al., "A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-ratecontrolled output buffer," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 762-768, 2003. https://doi.org/10.1109/JSSC.2003.810030
  5. L. Wang, L. Liu, and H. Chen, "An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL," IEEE Trans. Circuits and Systems II, vol. 57, No. 6, Jun 2010, pp 421-425. https://doi.org/10.1109/TCSII.2010.2048379
  6. R. Yang, S. Liu, "A 2.5 GHz all-digital delaylocked loop in $0.13{\mu}m$ CMOS technology," IEEE J. Solid-State Circuits, vol. 42, No. 11, 2007, pp. 2338-2347. https://doi.org/10.1109/JSSC.2007.906183
  7. J.-T. Kwak et al., "A low cost high performance register-controlled digital DLL for 1Gbps x32 DDR SDRAM," Dig. Tech. Papers, VLSI Circuits Symp. pp. 112-113, 2002
  8. G-K Dehng, J-W Lin, S-I Liu, "A fast-lock mixedmode DLL using a 2-b SAR Algorithm," IEEE J. Solid-State Circuits, vol. 36, pp. 1464-1471, 2001. https://doi.org/10.1109/4.953474
  9. J. Kim, S. Lee, T. Jung, C. Kim, S. Cho, and B. Kim, "A low-jitter mixed-mode DLL for highspeed DRAM applications," IEEE J. Solid-State Circuits, vol. 35, pp. 1430-1436, Oct. 2000. https://doi.org/10.1109/4.871319
  10. Jong-Chern Lee et al., "A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM," IEEE Asian Solid State Circuits Conference, pp. 157-160, 2011.
  11. S. Sidiropoulos, et al., "A semidigital dual delaylocked loop," IEEE J. Solid-State Circuits, vol. 32, pp. 1683-1692, Nov. 1997. https://doi.org/10.1109/4.641688
  12. Sangwoo Han and Jongsun Kim, "A highresolution wide-range dual-loop digital delaylocked loop using a hybrid-search algorithm," IEEE Asian Solid State Circuits Conference, pp. 293-296, 2012.