JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

  • Kim, Sung-Yong (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Jin, Xuefan (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Chun, Jung-Hoon (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Kee-Won (College of Information & Communication Engineering, Sungkyunkwan University)
  • Received : 2016.02.27
  • Accepted : 2016.06.06
  • Published : 2016.08.30
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Abstract

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

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References

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