JSTS:Journal of Semiconductor Technology and Science

  • 제16권3호
  • /
  • Pages.261-273
  • /
  • 2016
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

Reconfigurable FIR Filter for Dynamic Variation of Filter Order and Filter Coefficients

  • Meher, Pramod Kumar (School of Computer Engineering, Nanyang Technological University) ;
  • Park, Sang Yoon (Department of Electronic Engineering and MPEES-ARC, Myongji University)
  • 투고 : 2015.06.30
  • 심사 : 2016.01.20
  • 발행 : 2016.06.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) full-parallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.

키워드

참고문헌

  1. T. Hentschel, M. Henker, and G. Fettweis, "The digital front-end of software radio terminals," IEEE Personal Commun. Mag., vol. 6, no. 4, pp. 40-46, Aug. 1999. https://doi.org/10.1109/98.788214
  2. K.-H. Chen and T.-D. Chiueh, "A low-power digit-based reconfigurable FIR filter," IEEE Trans. Circuits Syst. II, vol. 53, no. 8, pp. 617-621, Aug. 2006. https://doi.org/10.1109/TCSII.2006.875373
  3. L. Ming and Y. Chao, "The multiplexed structure of multi-channel FIR filter and its resources evaluation," 2012 International Conference on Computer Distributed Control and Intelligent Environmental Monitoring (CDCIEM), Mar. 2012.
  4. I. Hatai, I. Chakrabarti, and S. Banerjee, "Reconfigurable architecture of a RRC FIR interpolator for multi-standard digital up converter," Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), IEEE 27th International, May, pp. 247-251.
  5. R. Mahesh and A. P. Vinod, "Low complexity flexible filter banks for uniform and non-uniform channelisation in software radios using coefficient decimation," Circuits, Devices Systems, IET, vol. 5, no. 3, pp. 232-242, May 2011. https://doi.org/10.1049/iet-cds.2010.0010
  6. E. Ozalevli, W. Huang, P. E. Hasler, and D. V. Anderson, "A reconfigurable mixed-signal VLSI implementation of distributed arithmetic used for finite-impulse response filtering," IEEE Trans. Circuits Syst. I, vol. 55, no. 2, pp. 510-521, Mar. 2008. https://doi.org/10.1109/TCSI.2007.913735
  7. P. K. Meher, S. Chandrasekaran, and A. Amira, "FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic," IEEE Trans. Signal Process., vol. 56, no. 7, pp. 3009-3017, Jul. 2008. https://doi.org/10.1109/TSP.2007.914926
  8. S. Y. Park and P. K. Meher, "Efficient FPGA and ASIC realizations of DA-based reconfigurable FIR digital filter," IEEE Trans. Circuits Syst. II, vol. 60, no. 7, pp. 511-515, Jul. 2014.
  9. M. Kumm, K. Moller, and P. Zipf, "Dynamically reconfigurable FIR filter architectures with fast reconfiguration," Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 8th International Workshop on, Jul. 2013.
  10. M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, "Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 2, pp. 151-165, Feb. 1996. https://doi.org/10.1109/43.486662
  11. A. G. Dempster and M. D. Macleod, "Use of minimum-adder multiplier blocks in FIR digital filters," IEEE Trans. Circuits Syst. II, vol. 42, no. 9, pp. 569-577, Sep. 1995. https://doi.org/10.1109/82.466647
  12. A. P. Vinod, A. Singla, and C. H. Chang, "Low-power differential coefficients-based FIR filters using hardware-optimised multipliers," Circuits, Devices Systems, IET, vol. 1, no. 1, pp. 13-20, Feb. 2007. https://doi.org/10.1049/iet-cds:20050324
  13. P. Tummeltshammer, J. C. Hoe, and M. Puschel, "Time-multiplexed multiple-constant multiplication," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 9, pp. 1551-1563, Sep. 2007. https://doi.org/10.1109/TCAD.2007.893549
  14. R. Mahesh and A. P. Vinod, "New reconfigurable architectures for implementing FIR filters with low complexity," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 2, pp. 275-288, Feb. 2010. https://doi.org/10.1109/TCAD.2009.2035548
  15. M. Faust, O. Gustafsson, and C.-H. Chang, "Reconfigurable multiple constant multiplication using minimum adder depth," Signals, Systems and Computers (ASILOMAR), Conference Record of the Forty Fourth Asilomar Conference on, Nov. 2010, pp. 1297-1301.
  16. S.-F. Hsiao, J.-H. Z. Jian, and M.-C. Chen, "Low-cost FIR filter designs based on faithfully rounded truncated multiple constant multiplication/accumulation," IEEE Trans. Circuits Syst. II, vol. 60, no. 5, pp. 287-291, May 2013. https://doi.org/10.1109/TCSII.2013.2251958
  17. P. K. Meher and S. Y. Park, "Area-delay-power efficient fixed-point LMS adaptive filter with low adaptation-delay," IEEE Trans. VLSI Syst., vol. 22, no. 2, pp. 362-371, Feb. 2014. https://doi.org/10.1109/TVLSI.2013.2239321
  18. P. K. Meher and S. Y. Park, "Critical-path analysis and low-complexity implementation of LMS adaptive algorithm," IEEE Trans. Circuits Syst. I, vol. 61, no. 3, pp. 778-788, Mar. 2014. https://doi.org/10.1109/TCSI.2013.2284173
  19. P. K. Meher and S. Y. Park, "High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic," VLSI and System-on-Chip (VLSI-SoC), IEEE/IFIP 19th International Conference on, Oct. 2011, pp. 428-433.
  20. D. J. Allred, H. Yoo, V. Krishnan, W. Huang, and D. V. Anderson, "LMS adaptive filters using distributed arithmetic for high throughput," IEEE Trans. Circuits Syst. I, vol. 52, no. 7, pp. 1327-1337, Jul. 2005. https://doi.org/10.1109/TCSI.2005.851731
  21. S. H. Yoon and M. H. Sunwoo, "An efficient variable-length tap FIR filter chip," Design Automation Conference. Proceedings of the ASP-DAC '98. Asia and South Pacific, Feb. 1998, pp. 157-161.
  22. S.-J. Lee, J.-W. Choi, S. W. Kim, and J. Park, "A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption," IEEE Trans. VLSI Syst., vol. 19, no. 12, pp. 2221-2228, Dec. 2011. https://doi.org/10.1109/TVLSI.2010.2088142
  23. F. Sheikh, M. Miller, B. Richards, D. Markovic, and B. Nikolic, "A 1-190Msamples/s 8-64 tap energyefficient reconfigurable FIR filter for multimode wireless communication," Proc. 2010 IEEE Symposium on VLSI Circuits (VLSIC), Jun. 2010, pp. 207-208.
  24. K. K. Parhi, VLSI Digital Signal Procesing Systems: Design and Implementation. New York: John Wiley & Sons, Inc, 1999.
  25. J. G. Proakis and D. G. Manolakis, Digital Signal Processing: Principles, Algorithms and Applications. Upper Saddle River, NJ: Prentice-Hall, 1996.
  26. D. A. Parker and K. K. Parhi, "Low-area/power parallel FIR digital filter implementations," J. VLSI Signal Process. Syst., vol. 17, no. 1, 1997.
  27. "Synposys, Inc., DesignWare Building Block IP User Guide, 2012.06-SP2, Mountain View, CA." [Online]. Available: http://www.synopsys.com/
  28. C. J. Nicol, P. Larsson, K. Azadet, and J. H. O'Neill, "A low-power 128-tap digital adaptive equalizer for broadband modems," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1777-1789, Nov. 1997. https://doi.org/10.1109/4.641700