I. INTRODUCTION
In recent years, renewable energy sources have become more and more widely used to replace fossil fuel in many industrial applications. However, such applications include fuel-cell energy-conversion systems and solar-cell energy-conversion systems, where the voltage obtained from the fuel or PV cells is low, so that there is not enough DC voltage to feed the AC utility. In addition, the automobile high-intensity-discharge headlamp operating voltage is much higher than that provided by a battery [1]-[5]. Therefore, it is necessary to step up from a low voltage to a high voltage.
In the conventional converter, a boost converter is used for voltage step-up applications. This is due to the fact that a boost converter can provide a high step-up voltage gain with an extreme duty cycle in theory. However, in practice, the boost converter voltage gain is usually restricted by the effects of the power switch, rectifier diode, and equivalent series resistance (ESR) of the inductor and capacitor. Moreover, extremely high duty ratio operation will result in serious reverse-recovery problems, low efficiency, high voltage stress of the switch, and electromagnetic interference (EMI) problems [6]-[8]. Thus, a high step-up converter is used for these applications.
Many topologies have been proposed to improve conversion efficiency and to achieve a high step-up voltage gain [7]-[21].A high step-up voltage gain can be obtained by a switched capacitor technique [7], [8]. Unfortunately, the main switch has a high surge current, the conduction loss is increased, and the cost is increased. Switched inductor technology also extends the voltage gain [7], [9]. Unfortunately, the voltage stresses of the switches of converters are still higher. Therefore, high-voltage rated switches induce serious conduction losses. The voltage-lift technique [10]-[12] developed by Luo can also achieve a high step-up voltage gain. The voltage-lift technique is similar to the Cuk converter, and is based on an energy transfer from one inductor via an intermediate capacitor to the output. However, the main switch suffers from a high transient current, and the conduction loss is increased.
Converters can achieve a high step-up voltage gain by adjusting the turns ratio of the coupled inductor [13]. Unfortunately, the leakage inductance of the coupled-inductor causes a high voltage spike on the active switches when the switches are turned off [13]-[16]. As a result, converters using a coupled-inductor with an active-clamp circuit and a passive-clamp circuit have been proposed [17]-[21]. Moreover, the leakage energy can be recycled with the help of the clamp circuit.
In this paper, two novel voltage-lift cells are proposed. These cells integrate three-winding coupled inductors technology and switched-capacitor technology, and further extend the voltage gain. At the same time, this paper proposes a novel high step-up voltage gain and a clamp-mode converter which uses a SCIC to achieve a high step-up voltage gain and to reduce the voltage stress of the main switch. The SCIC shares its capacitor with a clamping circuit. Additionally, two capacitors can be charged in parallel and discharged in series via the coupled inductor. However, the leakage inductor of the coupled inductor may cause a high power loss and a voltage spike. Thus, a passive clamping circuit can recycle the leakage-inductor energy of the coupled inductor and clamp the voltage across the main switch. Thus, the reverse-recovery problems in the diodes are alleviated, and the performance of the proposed converter is improved.
II. VOLTAGE-LIFT-TYPE SWITCHED-COUPLED-INDUCTOR-CAPACITOR CELLS
The basic step-up switched-capacitor cells (SC) are constituted with two capacitors and two diodes as shown in Fig. 2. The following are for the discussion about Fig. 1(a), and Fig. 1(b) is similar to Fig. 1(a). When the switching is turned on, D1 and D2 turn off, while C1 and C2 are discharged in series. When the switching is turned off, D1 and D2 turn on, while C1 and C2 are charged in parallel.
Fig. 1.Step-up basic switching structures. (a) Up I. (b) Up II.
Fig. 2.Switching topologies of the step-up structures. (a) Up I. (b) Up II.
Converters with switched capacitor (SC) cells can improve the voltage gain when compared to the classic boost converter. Unfortunately, [22] and [23] have a higher components count, their cost is increased, and their output voltages are not continuously adjustable. In recent years, converters with coupled inductors have become more and more widely used in order to solve these problems. These converters can achieve a higher step-up voltage gain by adjusting the turns ratio of the coupled inductor, which can reduce the number of the active switches when compared with converters with SC cells. Unfortunately, the leakage inductance of a coupled-inductor results in a high voltage spike on active switches when the switches are turned off. [24] and [25] with coupled inductors can achieve a high step-up voltage gain and the leakage-inductor energy can be recycled to the load. However, in [24] the voltage gain is only equal to 8 and the voltage stress of the output diode is beyond 0.5 Vo when n = 2 and D = 0.5 . In [25] the voltage gain is only equal to 2 and the voltage stress of the output diode is equal to 0.5 Vo when n = 2 and D = 0.5 .In order to further improve the voltage gain, reduce the number of active switches, and reduce the voltage stress of the output diode, the SCICs are proposed in this paper.
The voltage-lift technique is then applied to basic SC cells, which can generate new voltage-lift-type SCIC structures with a higher voltage transfer gain. The basic step-up SCIC structures formed with windings-coupled inductors, diodes and capacitors are shown in Fig. 3. For the convenience of analysis, the switching operations of the proposed SCIC structures are shown in Fig. 4. As shown in Fig. 3(a), the secondary-sides of the windings-coupled inductor are inserted into two branches with the capacitor. The current-flow path is shown in Fig. 4(a). When the switching topologies Ton , D3 turns on, D1 and D2 turn off, and L2 , L3 , C1 and C2 are discharged in series. When the switching topologies are turned off, D1 and D2 turn on, D3 turns off, and the voltage-lift branch ( L2 and C1 ) is charged with the voltage-lift branch ( L3 and C2 ) in parallel. Fig. 3(b) is similar to Fig. 3(a) in terms of operating principle, and the current-flow path is shown in Fig. 4(b).
Fig. 3.The proposed basic step-up switching structures. (a) Up I. (b) Up II.
Fig. 4.The current-flow path with the proposed step-up structures. (a) Up I. (b) Up II.
III. PROPOSED CONVERTER AND OPERATIONAL PRINCIPLE
Basic step-up switched-capacitor cells (SC) are constituted with two capacitors and two diodes as shown in Fig. 2. The converter with the SCIC led in Fig. 3(b) has not been discussed due to its similarity to Fig. 5(a). The proposed converter with the SCIC Up I is illustrated in Fig. 5(a), which contains an active switch S , three-winding-coupled inductors, three rectifier diodes D1 , D2 and Do , and three capacitors C1 , C2 and Co . It is clear that the leakage inductance of the coupled-inductor will cause a high voltage spike on switch S when the switch is turned off.
Fig. 5.Circuit configure of the proposed converter.
In order to suppress the voltage spike by the leakage inductor, clamping circuits composed of diodes D3 and D4 and capacitors C1 and C2 are shown in Fig. 5(b).Diodes D3 and D4 are used to clamp switch S to and prevent the problem of the same time conduction between D1 and Do .
The equivalent circuit is shown in Fig. 7. The coupled inductor is modeled as a magnetizing inductor Lm , a primary leakage inductor Lk , and ideal transformers with turns ratios of N = N2 : N1 = N3 : N1 (N > 1), where N1 , N2 and N3 are the primary-side turns and the secondary-side turns, respectively. VL2 is equal to VL3 , and capacitor CS is the parasitic capacitor of switch S . To simplify the circuit analysis of the proposed converter, the following conditions are assumed. First, all of the components are ideal. The ON-state resistance RDS of the active switches, the forward voltage drop of the diodes and the ESR of the coupled inductor and all of the capacitors are ignored. Second, capacitors Co , C1 and C2 are sufficiently large, the voltages VC1 and VC2 are equal to VCC , and the voltages across the capacitors are considered to be constant during one switching period. Fig. 6 shows typical waveforms during one switching period in continuous-conduction-mode (CCM) operation. The operating principle is described as follows:
Fig. 6.Some typical waveforms of proposed converter at CCM operation.
Fig. 7.Equivalent circuit model of the proposed converter.
1) Mode I [ t0 , t1 ]: At t = t0 , The active switch S is turned on. Do , D3 and D4 are turned off. The current-flow path is shown in Fig. 8(a). During this time interval, the magnetizing inductor Lm and the leakage inductor Lk are charged by the input source and the currents iLm and iLk are increased. At the same time, the energy of the input source is released to capacitors C1 and C2 via the secondary winding L2 and L3 of the coupled inductor, respectively, and the currents iL2 and iL3 are increased. The output capacitor Co provides energy to the load R . The voltages across VL2 and VL3 are clamped at VCC . The voltage VDo is equal to Vo . Moreover, the energy stored in CS is rapidly and completely discharged. This operating mode ends when the currents iL2 and iL3 are equal to zero at t = t1 .
Fig. 8.Current-flow path of the operating modes during one switching period at CCM operation. (a) Mode I. (b) Mode II. (c) Mode III. (d) Mode IV. (e) Mode V.
2) Mode II [ t1 , t2 ]: During this time interval, the active switch S is still turned on. D1 - D4 are turned off. The current-flow path is shown in Fig. 8(b). The dc-source Vin energy is transferred to Lm and Lk through switch S . Therefore, the currents iLm and iLk are increased. Meanwhile, C1 , C2 , L2 and L3 are series connected to transfer their energies to Co and the load R via Do . The currents iL2 , iL3 and iC1 are increased. This operating mode ends when switch S starts to turn off at t = t2 .
3) Mode III [ t2 , t3 ]: At t = t2 , switch S is turned off. The current-flow path is shown in Fig. 8(c). During this mode, the voltage across switch S increases rapidly. The voltages across L2 and L3 are clamped at (Vo - Vcc )/2 , and the voltage across the active switch S is clamped at Vcc , because the clamping diodes D3 and D4 are turned on. The voltages across D1 and D2 are clamped at VL2 and VL3 , respectively. As a result, they are reverse-biased. The energies of inductors L2 and L3 with capacitors C1 and C2 are released to the output capacitor Co and the load R . The voltage VL1 is equal to Vin - Vcc . This operating mode ends when the current iL2 becomes zero at t = t3 .
4) Mode IV [ t3 , t4 ]: At t = t3 , the output diode is turned off, and the rectifier diodes D1 and D2 are turned on. The current-flow path is shown in Fig. 8(d). The voltage across L1 is still equal to Vin - Vcc , and the voltages across L2 and L3 are clamped at - Vcc . However, the voltage across switch S is clamped at Vcc . The primary side of the coupled inductor is in series with the input source and the secondary side L2 of the coupled inductor to release their energies to the capacitor C1 via the diode D1 . At the same time, the primary side of the coupled inductor is in series with the input source and the secondary side L3 to release their energies to the capacitor C2 via the diode D2 , and the currents iLk , iLm and iL2 are reduced. Thus, the clamping diodes D3 and D4 are cut off at t = t4 , and this operating mode ends.
5) Mode V [ t4 , t5 ]: During this time interval, switch S is still turned off. The clamping diodes D3 and D4 are turned off, and the current-flow path is shown in Fig. 8(e). The primary side of the coupled inductor, the secondary side winding L2 and the input source are in series to transfer their energies to the capacitors C1 via the rectifier diode D1 . Meanwhile, the capacitor C2 is charged by the input source, the primary side of the coupled inductor and the secondary side winding L3 via the rectifier diode D2 . This mode ends at t = t5 when switch S is turned on at the beginning of the next switching period.
IV. STEADY-STATE ANALYSIS
A. CCM Operation
In CCM operation, the time durations of modes I, III and IV are very short when compared to one switching period. Thus, only modes II and V are considered. In order to analyze the voltage gain of the proposed converter, the voltages across the capacitors C1 and C2 are assumed to be:
The coupled-coefficient k and the turns ratio n of the coupled-inductor are assumed to be:
During mode II, the following equations can be written based on Fig. 8(b):
Substituting (4) into (5), the voltages of the capacitors C1 and C2 are obtained as:
During mode V, the following equations can be formulated based on Fig. 8(e):
Where the voltage is found to be:
Using the volt–second balance principle on L1 yields:
Substituting (4) and (8) into (9), the voltages across the capacitors C1 and C2 and the voltage gain are obtained as:
It can be seen that the voltage gain is influenced by the turns ratio and the leakage coefficient. The relationships between the voltage gain, the duty ratio and the coupling coefficients of the coupled inductor are shown in Fig. 9. It can be seen that the voltage gain is less sensitive to the coupling coefficient. Thus, if the impact of the leakage inductances of the coupled inductor is neglected, the coupled coefficient k is equal to 1. The ideal voltage gain can be simplified as:
Fig. 9.Voltage gain versus duty ratio at CCM operation under n = 2 and various k .
The voltage gain of a traditional boost converter is 1/ (1 - D). In [7], the basic switch-capacitor boost voltage gain is 1 + D / (1 - D) . The voltage gain in [20] is (1 + nD) / (1 - D) and the voltage gain in [21] is (1 + 2n - nD) / (1 - D) . They have a lower voltage gain when compared with the proposed converter.
B. Boundary Operating Condition
Since the time durations [ t0 , t1 ] and [ t2 , t4 ] are very short when compared to one switching period, these two time durations are not considered. When the proposed converter is operated in the boundary conduction mode, the peak value of the secondary side current of the coupled inductor is given as:
Thus, the peak current of the output diode is given as
At the steady state, the average value of iDo is equal to Io . Thus:
Then, the time constant τL2 of the secondary side for the coupled inductor is derived as:
Where fs is the switching frequency.
Substituting (11) and (16) into (15), the boundary time constant τL2B for the secondary side of the coupled inductor can be given as:
If τL2 is larger than τL2B , the proposed converter is operated in the CCM. The curved line of τL2B is shown in Fig. 10.
Fig. 10.Boundary condition of the proposed converter with n=2 and k=1.
C. Voltage and Current Stresses on Power Devices
According to the operating principle, the voltage and current stresses on power devices are discussed as follows. If the impact of the leakage inductor of the coupled inductor is ignored, the voltage stresses on switch S , D1 - D3 and Do are given as:
From (14) and (15)the current stresses that flow through D1 , D2 and Do are found to be:
In order to simplify the current calculation, the extremely short time intervals [t0 - t1] , [t2 - t3] and [t3 - t4] are ignored. The magnetizing current is considered to be a constant since the magnetizing inductor LM is large enough. The simplified waveforms of the proposed converter are shown in Fig. 11.
Fig. 11.Simplified waveforms.
According to the current balance law, the on-state average current of capacitor C1 can be expressed as:
According to the current balance law, the off-state average currents of capacitor C1 and diodes D1 and D2 can be represented as:
Thus, based on Fig.11 and equation (24), the magnetic average current of the coupled inductor can be represented as:
D. Performance Comparison
To further demonstrate the performance of the proposed converter, Table I shows a comparison of the performances between the voltage-clamped DC–DC converter in [26], the coupling inductor boost converter in [27], the coupled inductor voltage-lift converter in [28], the coupled inductor active-network converter in [29], the coupled inductor voltage doubler cell converter in [30],and the proposed converter.
TABLE IPERFORMANCE COMPARISONS AMONG DIFFERENT CONVERTERS
The voltage gain of the proposed converter is compared with that of the step-up converters in Fig. 12 when N = 2 and K = 1. It is observed that the voltage gain of the proposed converter is higher than that of the others.
Fig. 12.Voltage gain comparison.
The relationship between the voltage stress of the active switch and variable duty cycle is described in Fig. 13 when N = 2 . The active switch stress of the proposed converter is lower to under D < 0.5 .
Fig. 13.Active switch voltage stress comparison.
The relationship between the voltage stress of the output diode with a variable duty cycle is shown in Fig. 14 when the turns ratio is equal to 2. When the duty cycle is more than about 0.5, the output diode voltage stress of the proposed converter is lower.
Fig. 14.Output diode voltage stress comparison.
Compared to the voltage-clamped DC–DC converter in [26], with the same component count, the voltage gain of the proposed converter has an advantage, and the output diode voltage stress of the proposed converter is lower when the duty cycle is beyond 0.5. When the duty cycle is less than 0.5, the output diode voltage stress of the converter in [26] is lower. Fortunately, the proposed converter has an obviously advantage in terms of the active switch voltage stress. Therefore, low RDS MOSFETs can be used. This is beneficial for improving the converter efficiency.
Comparing the coupling inductor boost converter in [27], the diode count of the presented converter is greater.
However, the active switch count is lower and the voltage gain of the presented converter has an advantage. The output diode voltage stress is equal to the presented converter. When the duty cycle is beyond about 0.72 the active switch voltage stress of the presented converter is more than the converter in [27]. When the duty cycle is lower than 0.72 the active switch voltage stress has an advantage especially when the duty cycle is lower than 0.5. In this paper, the duty cycle is about 0.4.Therefore, low RDS MOSFETs can be used.
Compared to the coupled inductor voltage-lift converter in [28], the proposed converter has more diodes. Fortunately, the voltage gain and the output diode voltage stress of the presented converter have advantages. When the duty cycle is more than about 0.5, the active switch voltage stress has no advantage. However, the active switch voltage stress is lower when the duty cycle is less than 0.5. In this paper, the duty cycle is about 0.4. Therefore, low RDS MOSFETs can be used.
Compared to the coupled inductor active-network converter in [29], the voltage gain and active switch voltage stress of the proposed converter have advantages. In addition, the output diode voltage stress of the proposed converter is lower when the duty cycle is beyond about 0.27, and the proposed converter has fewer diodes and switches.
Compared to the coupled inductor voltage doubler cell converter in [30], the voltage gain and output diode voltage stress of the proposed converter have advantages. The active switch voltage stress is low when D < 0.5 , and the active switch count of the proposed converter is lower.
V. EXPERIMENTAL RESULTS
To verify the performance of the proposed converter, a prototype circuit is implemented in the laboratory. Table II shows the system specifications of the proposed converter, and Table III shows the component specifications used in the proposed converter. The specifications are as follows:
TABLE IISYSTEM SPECIFICATIONS OF THE PROPOSED CONVERTER
TABLE IIISYSTEM SPECIFICATIONS OF THE PROPOSED CONVERTER
A. The magnetizing inductance design
The magnetizing inductor can be designed by setting an acceptable current ripple on the magnetizing inductor, which is given by:
By combining (25) and (26), and collecting the terms, the magnetizing inductance can be computed as:
Where KLM is the current ripple coefficient.
Based the relative equation in section V, the numerical design of the magnetizing inductance of the coupled inductor, the output capacitor and the clamped capacitors are shown as:
B. Turns ratio design
Since the turns ratio of the coupled inductor determines the voltage stress of the switch and the operational duty-cycle of the converter, it is the key parameter in the circuit design. The turns ratio can be obtained when the duty-cycle is constant, which is given by:
Some of the key figures are given as Fig. 15 under a full-load. Fig. 15 shows the measured waveforms for a full-load. The proposed converter is operated in the CCM. The waveforms demonstrate that the steady-state analysis is correct. In the measured waveforms, the duty cycle is 41% and the voltage stress on switch S is equal to 35V during the switch off and it is shortly clamped at 54V. Therefore, a low-voltage-stress switch is adopted to achieve high efficiency for the proposed converter. Fig. 15(a) shows the switch voltageVS,the coupled inductor currents iL1 ,and iL2 . The waveforms agree with the theoretical analysis. Fig. 15(b) shows the switch voltageVS, the coupled inductor voltage VL1 ,and the clamped diode reverse-biased voltage VD3 . Fig. 15(c) shows the switch voltage VS , the clamped diode current iD3 , and the output diode current iDo . Fig. 15(d) shows that the output voltageVS is equal to 197V.
Fig. 15.Experimental waveforms of proposed converter under full-load 200W.
Fig. 16 shows the conversion efficiency of the proposed converter, where the maximum efficiency is around 95.8% at Po = 80 W, and the full-load efficiency is approximately 93.7% under 200W with a 20V input voltage.
Fig. 16.Experimental conversion efficiency
VI. CONCLUSION
In this paper, a novel switched-coupled-inductor-capacitor topology with a high voltage ratio is proposed and the steady state analysis is given. A passive lossless clamping circuit is introduced to suppress voltage spikes across the switch. Compared to traditional high step-up DC-DC converters, it has following main advantages:
(1) A high voltage gain can be achieved with a reduced magnetic size.
(2) A single active switch is required, implying a very simple control circuit. The inrush current problem of the switched-capacitor circuit is well restrained by the leakage inductance of the coupled inductor.
(3) A low voltage stress power switch can be selected, which can help reduce both the on-state resistance of the switch and the loss.
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피인용 문헌
- Transformer Less High Voltage Gain Step-Up DC-DC Converter Using Cascode Technique vol.117, 2017, https://doi.org/10.1016/j.egypro.2017.05.105
- Interleaved High Step-Up DC-DC Converter Based on Voltage Multiplier Cell and Voltage-Stacking Techniques for Renewable Energy Applications † vol.11, pp.7, 2018, https://doi.org/10.3390/en11071632
- Design and Implementation of New Topology for Nonisolated DC–DC Microconverter with Effective Clamping Circuit pp.1793-6454, 2018, https://doi.org/10.1142/S0218126619500828