References
- M.H. Kim, I.K. Han, Y. Joo, S.S. Lim, "Design and Implementation of Nonvolatile Memory-Based Cache Simulators," Proceedings of Korea Computer Congress, Vol. 42, No. 1, pp. 1498-1500, 2015 (in Korean).
- Y. Zhang, S.B. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, H.S.P. Wong, "An integrated phase change memory cell with Ge nanowire diode for cross-point memory," Proceedings of IEEE Symposium on VLSI Technology, pp. 98-99, 2007.
- S. Chung, K.M. Rho, H.J. Suh, D.J. Kim, H.J. Kim, S.H. Lee, J.H. Park, H.M. Hwang, S.M. Hwang, J.Y. Lee, Y.B. An, J.U. Yi, Y.H. Seo, D.H. Jung, M.S. Lee, S.H. Cho, J.N. Kim, G.J. Park, G. Jin, A.D. Smith, V. Nikitin, A. Ong, X. Tang, Y. Kim, J.S. Rho, S.K. Park, S.W. Chung, J.G. Jeong, S.J. Hong, "Fully Intergrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application," Proceedings of IEEE International Electron Devices Meeting, pp. 12.7.1-12.7.4, 2010.
- A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, Y. Hayakawa, K. Tsuji, S. Yoneda, A. Himeno, K. Shimakawa, T. Takagi, T. Mikawa, K. Aono, "An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput," IEEE Journal of Solid-State Circuits, Vol. 48, No. 1, pp. 178-185, 2013. https://doi.org/10.1109/JSSC.2012.2215121
- J. Yue, Y. Zhu, "Accelerating write by exploiting PCM asymmetries," Proceedings of IEEE 19th International Symposium on High Performance Computer Architecture, pp. 282-293, 2013.
- Y. Wang, Y. Han, L. Zhang, H. Li, X. Li, "ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing," Proceedings of the 52nd Annual Design Automation Conference, No. 47 pp. 1-6, 2015.
- R. Maddah, S. Mohammad, Seyedzadeh, R. Melhem, "CAFO: Cost aware flip optimization for asymmetric memories," Proceedings of IEEE 21st International Symposium on High Performance Computer Architecture, pp. 320-330, 2015.
- J. H. Lee, "PCM Main Memory for Low Power Embedded System," IEMEK J. Embed. Sys. Appl., Vol. 10, No. 6, pp. 391-397, 2015 (in Korean). https://doi.org/10.14372/IEMEK.2015.10.6.391
- Y. Kim, B. Tauras, A. Gupta, B. Urgaonkar, "FlashSim: A Simulator for NAND Flash-Based Solid-State Drives," Proceedings of IEEE 1st International Conference on Advances in System Simulation, pp. 125-131, 2009.
- V. Prabhakaran, T. Wobber, "SSD Extension for DiskSim Simulation Environment," Microsoft Resarch, Available: http://research.microsoft.com/en-us/downloads/b41019e2-1d2b-44d8-b512-ba35ab814cd4
- J. Gibson, R Kunz, D. Ofelt, M. Horowitz, J. Hennessy, M. Heinrich, "FLASH vs. (simulated) FLASH: closing the simulation loop," Proceedings of the 9th international conference on Architectural support for programming languages and operating systems, pp. 49-58, 2000.
- S.A. Herrod, "Using Complete Machine Simulation to Understand Computer System Behavior," Ph.D. thesis, 1998.
- P.S. Magnusson, B. Werner, "Efficient Memory Simulation in SimICS," Proceedings of the 28th Annual Simulation Symposium, pp. 62-73, 1995.
- T. Austin, E. Larson, D. Ernst, "SimpleScalar: an infrastructure for computer system modeling," Proceedings of IEEE Computer, Vol. 35, No. 2, pp. 59-67, 2002. https://doi.org/10.1109/2.982917
- J. Edler, M.D. Hill, Dinero IV Trace-Driven Uniprocessor Cache Simulator. Available: http://pages.cs.wisc.edu/-markhill/DineroIV
- Cachegrind: a cache and branch-prediction profiler Available: http://valgrind.org/docs/ manual/cg-manual.html
- M. Martonosi, A. Gupta, T. Anderson, "Tuning memory performance of sequential and parallel programs," Proceedings of IEEE Computer, Vol. 28, No. 4, pp. 32-40, 1995. https://doi.org/10.1109/2.375175
- Y. Joo, D. Jiu, X. Dong, G. Sun, N. Chang, Y. Xie, "Energy- and endurance-aware design of phase change memory caches," Proceedings of the Conference on Degign, Automation and Test in Europe, pp. 136-141, 2010.
- S. Cho, H. Lee, "Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance," Proceedings of IEEE 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 347-357, 2009.
- Y. Joo, S. Park, "A Hybrid PRAM and STT-RAM Cache Architecture for Extending the Lifetime of PRAM Caches," IEEE Computer Architecture Letters, Vol. 12 No. 2, pp. 55-58, 2013. https://doi.org/10.1109/L-CA.2012.24