JSTS:Journal of Semiconductor Technology and Science

  • 제16권1호
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  • Pages.70-79
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  • 2016
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

  • Park, Jun-Sang (Department of Electronic Engineering, Sogang University) ;
  • Jeong, Jong-Min (Department of Electronic Engineering, Sogang University) ;
  • An, Tai-Ji (Department of Electronic Engineering, Sogang University) ;
  • Ahn, Gil-Cho (Department of Electronic Engineering, Sogang University) ;
  • Lee, Seung-Hoon (Department of Electronic Engineering, Sogang University)
  • 투고 : 2015.07.17
  • 심사 : 2015.11.01
  • 발행 : 2016.02.28
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초록

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

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참고문헌

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