Journal of Electrical Engineering and Technology

  • 제11권6호
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  • Pages.1707-1713
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  • 2016
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  • 1975-0102(pISSN)
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  • 2093-7423(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
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Improved DC Offset Error Compensation Algorithm in Phase Locked Loop System

  • 투고 : 2015.12.17
  • 심사 : 2016.08.06
  • 발행 : 2016.11.01
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초록

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

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참고문헌

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