Analysis and Design of a DC-Side Symmetrical Class-D ZCS Rectifier for the PFC of Lighting Applications

Abstract

This paper proposes the analysis and design of a DC-side symmetrical zero-current-switching (ZCS) Class-D current-source driven resonant rectifier to improve the low power-factor and high line current harmonic distortion of lighting applications. An analysis of the junction capacitance effect of Class-D ZCS rectifier diodes, which has a significant impact on line current harmonic distortion, is discussed in this paper. The design procedure is based on the principle of the symmetrical Class-D ZCS rectifier, which ensures more accurate results and provides a more systematic and feasible analysis methodology. Improvement in the power quality is achieved by using the output characteristics of the DC-side Class-D ZCS rectifier, which is inserted between the front-end bridge-rectifier and the bulk-filter capacitor. By using this symmetrical topology, the conduction angle of the bridge-rectifier diode current is increased and the low line harmonic distortion and power-factor near unity were naturally achieved. The peak and ripple values of the line current are also reduced, which allows for a reduced filter-inductor volume of the electromagnetic interference (EMI) filter. In addition, low-cost standard-recovery diodes can be employed as a bridge-rectifier. The validity of the theoretical analysis is confirmed by simulation and experimental results.

I. INTRODUCTION

It is very well known that line current harmonic distortion causes several problems such as a voltage distortion, noise, heating that reduces efficiency, and reduced capacity of energy suppliers. In order to overcome these drawbacks, the need to comply with standards has forced the use of power-factor correction (PFC) in power converters. The development of high power-factor converters with minimized current total harmonics distortion (THDi) for lighting applications such as the electronic ballasts for gas-discharge lamps [1]-[18] and the drivers for light-emitting diodes (LED) [19]-[25] have to meet the lighting standard regulations of the International Electrotechnical Commission (IEC) 61000-3-2 Class-C limit for harmonic current emissions [26].

Recently, the use of resonant rectifiers for the PFC of single-stage converters has become attractive, due to the advantages of resonant-rectifier based PFC since a theoretical analysis can be used to provide a systematic, simple, and feasible solution. Examples of this are the zero-voltage-switching (ZVS) AC-side Class-E current-source driven rectifier for PFC (CECS-RPFC) [4], and the ZVS AC-side Class-DE current-source driven rectifier for PFC (CDECS-RPFC) [5], [8]. However, the main drawbacks of the previously proposed CECS-RPFC and CDECS-RPFC topologies are their low efficiency because they suffer from high current stresses in the power switches near the zero-crossing of the line voltage, and the fact that fast recovery diodes are required for the bridge-rectifier. As a result, these ballast topologies are unattractive for low-cost commercial applications. A ZVS DC-side asymmetrical CDECS-RPFC has been proposed in [9] and standard-recovery diodes can be used as a bridge-rectifier. The major problem with this technique is the high current stresses in the power switches, which results in low efficiency. Recently, a zero-current-switching DC-side asymmetrical Class-D current-source driven rectifier for PFC (CDCS-RPFC) has been proposed in [17] and it has greatly reduced current stress. However, the main disadvantage of this topology is the use of a large electromagnetic interference (EMI) filter due to the large high frequency ripple current of the line current. Therefore, it is very attractive to explore a single-stage PFC converter for lighting applications that has low current stresses, high efficiency and low cost.

The objective of this paper is to introduce a new topology for a resonant rectifier for PFC, called a DC-side symmetrical ZCS Class-D current-source driven rectifier. The efficiency of this circuit is higher than that of the other single-stage topologies, because the zero value of the driving-current near the zero-crossing of the line voltage can be obtained. The line current in the proposed symmetrical Class-D ZCS rectifier has twice the switching frequency when compared to the asymmetrical Class-D ZCS rectifier [17], which allows the switching ripple current to be removed with a smaller EMI filter. In additional, standard-recovery diodes can be used as the bridge rectifier. Thus, the cost can be reduced.

This paper is organized as follows. Section II presents the basic concepts of the proposed topology. In Section III, a circuit description is provided. The operating principle is reported in Section IV. A design example of the proposed topology is presented in Section V. Section VI gives a conduction loss analysis of the CDCS-RPFC. Simulation and experimental results to confirm the validity of the theoretical analysis and design procedure are presented in Section VII. Section VIII gives a discussion of the junction-capacitance effect of the CDCS-RPFC. Section IX gives some conclusions to summarize the merits of this paper.

 

II. PROPOSED TOPOLOGY

Various configurations for the DC-side CDCS-RPFC are shown in Fig. 1. The high-frequency current-source to drive a symmetrical CDCS-RPFC is supplied by the square-wave output voltage of the power converter through a matching network. Symmetrical CDCS-RPFC networks can be inserted on the AC-side, both the AC and DC side, or the DC-side without any restrictions as depicted in Fig. 1(a)-1(c), respectively. However, the symmetrical CDCS-RPFC can employ low-cost standard-recovery diodes as a bridge-rectifier due to the fact that the EMI filter is connected in cascade with the front-end bridge-rectifier. Circuit diagrams of the symmetrical CDCS-RPFCs, without considering the EMI filter, are depicted in Fig. 2(a)-2(c). In order to simplify the analysis of the DC-side symmetrical CDCS-RPFC, the input voltage is considered only in a positive half-cycle and the following assumptions are made: Fundamental-component approximation is used in the analysis of the rectifier with adequate accuracy.

Fig. 1.Circuit diagram of symmetrical CDCS-RPFCs.

Fig. 2.Family of symmetrical CDCS-RPFCs.

 

III. CIRCUIT DESCRIPTION

Fig. 3 shows a conceptual diagram of a DC-side symmetrical Class-D ZCS rectifier and an EMI filter. They are inserted between the front-end bridge-rectifier and the bulk-filter capacitor to increase the conduction angle of the bridge-rectifier diode current for obtaining a near unity power-factor and low line current harmonics distortion. In addition, a part of the DC-side Class-D ZCS rectifier performs the function of a pass device, in which the voltage difference, vO=VB-｜vin｜, dropped. Furthermore, it roughly matches the required basic characteristics for power-factor correction.

Fig. 3.Conceptual diagram of DC-side CDCS-RPFC for lighting applications.

The proposed ZCS CDCS-RPFC displayed in Fig. 2(c), consists of standard-recovery bridge-rectifier diodes, D1–D2–D3–D4, and fast-recovery diodes DD1 and DD2, which are the DC-side symmetrical CDCS-RPFC. The inverter semi-state, composed of two switches, M1 and M2, is supplied by a bulk-filter capacitor, CB, which is replaced by an ideal voltage source, since the DC-bus voltage, VB, across this capacitor is nearly constant. This results in constant lamp current amplitudes. The inverter is a Class-D ZVS resonant inverter, which has been presented in many studies [1], [27]. A matching network, Ld–Cd1–Cd2, is fed by a high-frequency square-wave voltage source from the Class-D ZVS resonant inverter. The square-wave voltage is converted into a high-frequency current source to drive the DC-side symmetrical CDCS-RPFC by the matching network. Additionally, two capacitors, Cd1 and Cd2, serve the functions of a filter capacitor and a coupling capacitor.

 

IV. PRINCIPLE OF THE TOPOLOGY

The operation principle of the DC-side symmetrical Class-D ZCS rectifier in the PFC semi-stage is displayed by the equivalent circuit shown in Fig. 4. The line voltage is represented as υin = VinsinωLt, where ωL is the line angular frequency. The bridge-rectifier output is a full-wave rectified sinusoidal voltage source ｜υin｜ = Vin｜sinωLt｜. The current waveform of the matching network that drives the DC-side symmetrical CDCS-RPFC is assumed to be a sine wave and is represented as id = Id sinωst, where ωs is the switching angular frequency. The driving-current, id = id1 = id2, is forced by the symmetrical matching network, Ld-Cd1–Cd2, which is illustrated in Fig. 2(c). It is assumed that the switching frequency, fs, is much higher than the line frequency, fL.

Fig. 4.Circuit derivation of PFC with DC-side symmetrical Class-D ZCS rectifier during positive half-cycle of line voltage.

Therefore, during the positive half-cycle of the line voltage, the full-wave rectified sinusoidal voltage source,｜υin｜, appears as a short circuit in the AC component. As shown in Fig. 4(a), the first driving current, id1, and the series capacitor, Cd1; and the second driving current, id2, and the series capacitor, Cd2, can be connected in parallel with the diode, DD1, and the diode, DD2, respectively. In addition, the parallel connection of DD1 with the series connection Cd1, id1; and the parallel connection of DD2 with the series connection Cd2, id2 are connected in series with the voltage source,｜υin｜. The sequence of these elements is interchangeable, as shown in Fig. 4(b). In this circuit, the DC-bus voltage source, VB, and the full-wave rectified sinusoidal voltage source,｜υin｜, are connected in series. Thus, these voltage sources can be combined into one voltage source, υO = VB -｜υin｜, as shown in Fig. 4(c). However, the output voltage of the Class-D ZCS rectifier is forced by the voltage source υO. This leads to a varying load resistance, RO, for the ZCS Class-D rectifier. The equivalent circuit of the DC-side symmetrical CDCS-RPFC during the negative half-cycle of the line voltage is similar to the equivalent circuit during the positive half-cycle of the line voltage. Thus, the explanations are omitted.

The current alternatively flows through diodes DD1 and DD2 when each diode is ON, as shown in Table I. The diodes begin to turn off when their current reaches zero to reduce the turn-off switching loss. The key waveforms of the current and voltage in one-switching cycle near the peak of the line voltage of the proposed circuit are illustrated in Fig. 5. Figure 6(a) shows a sinusoidal line voltage waveform in one line cycle. Fig. 6(b) show the full-wave rectified line voltage,｜υin｜, and the DC-bus voltage, VB, waveforms. Figure 6(c) shows the combined voltage, VB -｜υin｜, waveform. In these figures, if the instantaneous value of υin is positive and low, the output voltage of the Class-D ZCS rectifier, VB -｜υin｜, is high, and the rectifier-diode current is low. Thus, the average value of the rectifier diode current in one switching cycle is also low. Conversely, if the instantaneous value of υin is positive and high, the output of the Class-D ZCS rectifier, VB -｜υin｜, is low, and the rectifier-diode current is high. Thus, the average value of the diode current in one switching cycle is also high. Fig. 6(d) shows the driving-current, id, which is forced by the symmetrical matching network, Ld–Cd1–Cd2. The input-current waveform, iin, which is the filtered average diode current of the symmetrical Class-D ZCS rectifier, is displayed in Fig. 6(e). This waveform shows that the line current in the symmetrical Class-D ZCS rectifier has twice the switching frequency, which allows the switching ripple current to be easily removed with a smaller EMI filter. For the negative half-cycle of the line voltage, one can be considered to be the same as with the positive half-cycle of the line voltage.

TABLE IEQUIVALENT CIRCUIT OPERATION MODES IN ONE SWITCHING CYCLE OF SYMMETRICAL CDCS-RPFC.

Fig. 5.Key waveforms in one switching cycle of the Class-D ZCS rectifier.

Fig. 6.Conceptual waveforms in one line cycle of CDCS-RPFC.

Fig. 7 shows the circuit configuration of the new proposed single-stage electronic ballast with the DC-side symmetrical ZCS CDCS-RPFC. The principle of operation of the proposed circuit is illustrated by the equivalent circuit shown in Fig. 8. The input impedance of the Class-D ZCS rectifier is represented by an input resistor, Ri. The voltage transfer function, MV, [29] of this circuit, when the total conversion efficiency is assumed to be equal to 1, can be described by:

where ωr is the resonant frequency, and Q is the loaded quality factor of the matching network in the PFC stage. The range of MV is from zero to 1. The equivalent circuit in Fig. 8(a) can be divided into two parts. A simplified circuit of the CDCS-RPFC semi-stage and an equivalent circuit of the inverter semi-stage are illustrated in Figs. 8(b) and (c), respectively. The coupling capacitor, Cs, the resonant capacitor, Cr, and the lamp resistance, RLA, of the Class-D ZVS resonant inverter are converted to a series Rs–Crs circuit and the MOSFETs are modeled by switches with the on-resistances, rDS1 and rDS2. The resistances rLd and rLr represent the equivalent resistances of the inductors Ld and Lr, respectively. From Fig. 8(b), the minimum value of the load resistance, RO_min, occurs at the minimum output voltage, υO_min, as does the maximum output current, iO_max, of the Class-D ZCS rectifier.

Fig. 7.Circuit configuration of proposed topology for electronic ballast application.

Fig. 8.Equivalent circuits of proposed high-power-factor single-stage electronic ballast.

 

V. DESIGN OF THE PROPOSED TOPOLOGY

A design example is shown is this section to demonstrate the validity of the theoretical analysis. The proposed DC-side symmetrical CDCS-RPFC for electronic ballast applications can be divided into three parts: the PFC semi-stage, the ballast semi-stage and the EMI filter.

A. Design of the PFC Semi-Stage

The electronic ballast was designed to handle a line rms voltage, Virms, of 220 V and a line frequency, fL, of 50 Hz. It was assumed that the total ballast efficiency, η, was equal to 0.93. The ballast drew the sine wave input line current. The input power of the proposed DC-side symmetrical CDCS-RPFC is determined by:

where Pout is the output power of the fluorescent lamp when operated at a high frequency. The amplitude of the ballast input line current is calculated from:

It is assumed that the Class-D ZCS rectifier is driven by an ideal high-frequency sinusoidal current-source. When Iin = IOmax, the magnitude of the high-frequency driving-current at full load is:

The voltage ratio VB/Vin = 1.1 was chosen due to it providing a good tradeoff between an appropriate value of the harmonic distortion of line current, iin, and the voltage stress of the main switches, υDS ; the amplitude of the line voltage Vin = ≈ 311 V; and the DC-bus voltage VB ≈ 342 V. The input impedance of the Class-D ZCS rectifier at a full load, Ri_min, is obtained by:

From Fig. 8(b), the value of the inductance, Ld, is given from:

The switching frequency, fs, is 50 kHz. For a finite value of the capacitance Cd = Cd1 = Cd2, an additional La can be added to Ld to compensate for the reactance of Cd = 100 nF. The value of the additional inductance is given by:

The total inductance, Ld(total), is expressed as:

To achieve a ripple voltage of less than 1%, the value of the bulk-filter capacitor is determined by:

The E6 standard value of 68 μF is selected for CB.

B. Design of the Ballast Semi-Stage

The Class-D ZVS resonant inverter shown in Fig. 8(c), was designed by using the design procedure defined elsewhere [1], [28]. The switching frequency should be selected to be above the resonant frequency to ensure the ZVS condition. A 36-W fluorescent lamp (TLD36W/856) from Philips is used in this design. At startup, the resonant circuit operates with a high-quality factor that generates a high ignition voltage to strike the lamp. Because the lamp is high frequency driven, the steady-state lamp resistance is:

The relationship among the loaded-quality factor, QL, of the inverter semi-stage, the DC-bus voltage, VB, and the rms lamp voltage, VLA(rms), is described by:

The resonant inductor, Lr, is expressed as:

The resonant capacitor Cr is determined by:

The E6 standard value of 6.8 nF is selected for Cr. In order to simplify the design procedure, a close to parallel resonance was assumed. Therefore, the DC-blocking capacitor, Cs, is selected to be a hundred times the resonant capacitor, Cr, so that Cs is 0.68 μF.

C. Design of the EMI Filter

The design of the EMI filter in Fig. 7 can be found elsewhere [30]. The line current of the CDCS-RPFC consists of the high-frequency current components of the switching frequency, fs. Thus, a second order low-pass filter is employed at the DC-side of the bridge-rectifier to filter these high-frequency current harmonics. The upper limit capacitance of the filter capacitor, Cf_max, is calculated from:

where fL is the line frequency. It was assumed that the displacement power-factor, cosθ, was equal to 0.999. However, the filter capacitor, Cf, should be lower than Cf_max. Thus, a value of 50 nF is selected for Cf and represented as Cf = Cd1Cd2 / (Cd1 +Cd2). Finally, the filter inductor, Lf, is determined by:

where fc is the cut-off frequency, to ensure a low distortion, the cut-off frequency, fc, should be at least ten times lower than the switching frequency, fs.

 

VI. CONDUCTION LOSS ANALYSIS

The losses are generally divided into two parts: the conduction losses and the switching losses. However, the switching losses can be neglected, because the fast-recovery diodes, DD1 and DD2, are turn off under ZCS and the power MOSFETs, M1 and M2, are turned on under ZVS. Likewise, the conduction losses due to the parasitic resistance in the capacitors are very small. Therefore, their effects were neglected. The rms value of the resonant current in the ballast semi-stage, Ir,rms, is calculated from:

The power loss in each of the MOSFETs’ forward resistance, rDS, can be obtained as:

The converter uses MOSFETs (STMicroelectronics IRF740), with on-resistances, rDS, of 0.48 Ω. In case of the ZCS-RPFC [17], the envelope of the driving-current is an AM waveform with a modulation index of m = 0.33. The result has shown that the current stresses of the power MOSFETs have been significantly reduced when compared to the previously reported CECS-RPFC and CDECS-RPFC topologies [4], [5], [8], [9]. The bridge rectifier was built using standard-recovery diodes (Fairchild Semiconductor 1N4006) with a forward voltage drop of VD = 0.82 V. The power loss in each of the bridge rectifier diodes, D1–D4, due to the forward voltage, VD, is obtained as:

The DC-side symmetrical CDCS-RPFC was built using two fast-recovery diodes, DD1–DD2, (Fairchild Semiconductor UF4006) with a forward voltage drop of VD = 1.08 V. The power loss in these fast-recovery diodes, due to the forward voltage, VD, is:

The equivalent series resistance (ESR) of the filter inductor, rLf, is 1.432 Ω. Thus, the conduction loss in the filter inductor, PrLf, can be obtained as:

The ESR of the series inductor, rLd, is 0.093 Ω. Thus, the conduction loss in the inductor, PrLd, is obtained from:

The parasitic resistance of the resonant inductor, rLr, is 0.343 Ω. The conduction loss in the resonant inductor, PrLr, is obtained by:

 

VII. SIMULATION AND EXPERIMENTAL RESULTS

The proposed electronic ballast with the DC-side symmetrical CDCS-RPFC topology was constructed using the component values obtained from the above analysis. Summaries of the circuit parameters and components are presented in Table II. The switching frequency, fs, was fixed at 50 kHz. The line voltage was set to 220 Vrms, and the line frequency, fL, was 50 Hz.

TABLE IIPARAMETERS OF POWER CIRCUIT

A. Simulation Results

The proposed DC-side symmetrical CDCS-RPFC was simulated using PSpice to confirm the theoretical analysis. The simulation results of the input line current waveforms without the EMI filter of both the asymmetrical and the symmetrical CDCS-RPFCs are shown in Fig. 9. These waveforms show that the input line current in the DC-side symmetrical CDCS-RPFC has half the peak value and twice the switching frequency when compared to the DC-side asymmetrical CDCS-RPFC. Therefore, the ripple current of the DC-side symmetrical CDCS-RPFC can be removed by a smaller EMI filter. This large line input current is the main drawback of the DC-side asymmetrical CDCS-RPFC.

Fig. 9.Comparison of simulated waveforms of the input line current without EMI filter of asymmetrical and symmetrical CDCS-RPFCs; bottom two waveforms are zoomed-in views of top two waveforms.

Fig. 10 shows the simulated waveforms of the input line current and the driving current with and without the junction-capacitance effect. As can be seen, there is distortion in the line current waveform close to the zero crossing. This distortion occurs because the driving current, id, cannot reach zero due to the junction-capacitance effect of the Class-D ZCS rectifier diode. The waveform of the high frequency driving current, id, through the matching circuit is nearly a square-wave at the line’s zero crossing. The total harmonics distortion of iin versus the ratio of the maximum and minimum values of Id with variations of both the diode junction capacitance, Cj, and the switching frequency, fs, are shown in Fig. 11 and 12, respectively. It can be seen that the total harmonics distortion of iin depends on both the junction capacitance of the fast-recovery diodes used in the CDCS-RPFC and the switching frequency. Therefore, the selections of the fast-recovery diode and switching frequency have a significant impact on the line current harmonic distortion. The analysis is given in Section VIII.

Fig. 10.Comparison of simulated waveforms of input line current and driving current with and without junction capacitance effect; bottom two waveforms are zoomed-in views of middle two waveforms.

Fig. 11.Total harmonics distortion of iin versus ratio of maximum and minimum of Id and varied diode junction capacitance, Cj.

Fig. 12.Total harmonics distortion of iin versus ratio of maximum and minimum of Id and varied switching frequency.

B. Experimental Results

The measured line power was 36.4 W, while the input power-factor was approximately 0.98 as shown in Fig. 13. In this figure, there is distortion in the line current waveform close to the zero-crossing which is the same as in the simulation results.

Fig. 13.Measured waveforms of input line voltage and current.

The THD of the input line current THDi was 20.6% as depicted in Fig. 14. However, all of the measured harmonic components still satisfy the IEC 61000-3-2 Class-C standard. Fig. 15 and 16 display the experimental waveforms of the diode current, iDD1, and the diode voltage, υDD1, of the symmetrical CDCS-RPFC near the peak and the zero-crossing of the line voltage, respectively. As expected, the current peak of the diode current decreased as the instantaneous line voltage decreased, which roughly matches the required waveforms shown in Fig. 6. The experimental waveforms of the driving-current, id, at the no-load condition near the zero crossing and at the full-load condition near the peak of the line voltage are illustrated Fig. 17. The zero value of the driving-current near the zero crossing is obtained. The measured waveforms of the line voltage (Ch1), line current (Ch2), line power (Math1), lamp voltage (Ch3), lamp current (Ch4) and output power (Math2) are displayed in Fig. 18. The line power, Pin, was 36.5 W and the output power, Pout, was 34.2 W. The efficiency of the ballast was about 93.5%, indicating that a good efficiency can be obtained by using the proposed topology.

Fig. 14.Measured THD of iin from power analyzer.

Fig. 15.Measured waveforms of υDD1 and iDD1 near peak of line voltage; bottom two waveforms are zoomed-in views of top two waveforms.

Fig. 16.Measured waveforms of υDD1 and iDD1 near zero-crossing of the line voltage; bottom two waveforms are zoomed-in views of top two waveforms.

Fig. 17.Measured waveform of driving-current, id; lower waveform is a zoomed-in view of top waveform near peak of line voltage.

Fig. 18.Measured line voltage, line current, line power, lamp voltage, lamp current and lamp power waveforms.

 

VIII. DISCUSSION OF THE EFFECT OF THE PARASITIC CAPACITANCE OF THE CDCS-RPFC

To obtain the low line-current harmonic distortion at the zero-crossing of the line voltage, υin , the line current, iin, must equal to zero, which is the no-load condition of the CDCS-RPFC. In fact, the line current, iin, and the driving current, id, cannot reach zero near the zero-crossing of υin because of the junction capacitance effect [31] of the fast-recovery diodes, DD1 and DD2, of the Class-D rectifier as shown in Fig. 19(a). The junction capacitance is present in all of the reverse biased diodes because of the depletion region.

Fig. 19.Equivalent circuit of PFC semi-stage with parasitic capacitance effect of Class-D ZCS rectifier diode.

Therefore, the junction capacitors, Cj1 and Cj2, are modeled in parallel with the fast-recovery diodes, DD1 and DD2. It can be seen that the input impedance of the CDCS-RPFC cannot be modeled by a single equivalent input resistor, Ri. In the first simplified approach, the input impedance, Zi, of the CDCS-RPFC with the parasitic capacitance effect can be described by the parallel or series equivalent circuits [31] of the equivalent input resistor, Ri, with the equivalent input capacitor, Ci, and the input voltage is obtained from the square-wave output voltage of the Class-D inverter as shown in Fig. 19(b) and (c), respectively. From Fig. 19(b), it is well known that the voltage transfer function, MV, of the Class-D LCC series resonant parallel load inverter is more than 1. The ratio Vd/VDS2 versus fs/fr at various values of the quality factor Q is shown in Fig. 20. Therefore, near the zero-crossing of the line voltage, υin, DD1 can conduct current due to the fact that the voltage at its anode is more positive than the voltage at its cathode. As a result, the driving current, id, cannot reach zero. Accordingly, the selection of the fast-recovery diode as the CDCS-RPFC has a significant impact on the line current harmonic distortion. Diodes with a small Cj are preferred.

Fig. 20.Vd/VDS2 versus fs/fr at varied values of Q.

 

IX. CONCLUSION

This paper has presented the analysis, design and implementation of the DC-side symmetrical ZCS-CDCS-RPFC to improve the low power-factor and the high line current harmonic distortion for single-stage electronic ballast applications. The proposed topology combines a PFC stage based on a Class-D ZCS rectifier and an inverter stage based on a Class-D ZVS inverter into a single-stage power converter, making this technique attractive for commercial applications. However, this topology is only suitable for low power applications.

The design procedure is based on the principle of the symmetrical Class-D ZCS rectifier. The analysis, design and experimental results show that the proposed DC-side symmetrical ZCS-CDCS-RPFC for electronic ballast applications has the following characteristics:

The circuit operation was described and design equations were derived. A prototype designed for a T8-36W fluorescent lamp was built and tested to verify the theoretical analysis. The experimental results show that the single-state electronic ballast with a DC-side symmetrical CDCS-RPFC had a 0.98 power-factor, a 20.6% THDi, which is below the limit according to the IEC 61000-3-2 Class-C standard, and an efficiency of 93.5 %.